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Design Languages >> Verilog-AMS >> ADC Verilog-A Model Symbol View
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Message started by alexshel44 on Apr 28^th, 2020, 10:05am

Title: ADC Verilog-A Model Symbol View
Post by alexshel44 on Apr 28^th, 2020, 10:05am

Hello Everyone,

I am working through the book 'The Designer's Guide to Verilog-AMS' in chapter 3 listing 26 there is a model for an ideal ADC. I fully understand the code however I am having difficulties generating a symbol view in Virtuoso due to variable number of bits. If I instead set the number of bits to a constant everything seems to work properly.

When I generate the symbol view with the variable number of bits it gets an error on the output bin which is defined as out<0:bits-1> where bits is a variable.

Does anyone have any advice for how I can get this to work?

I'm not sure what versions are relevant but, I am using Virtuoso 6.1.7.

Thanks a lot,

Alex

Title: Re: ADC Verilog-A Model Symbol View
Post by alexshel44 on Apr 28^th, 2020, 10:11am

I just found the modification to this listing that is posted on this website. https://designers-guide.org/verilog-ams/dg-vams/ch3/ch3-listing26.tgz

I guess this is just a feature that doesn't work in spectre anymore. Does anyone have more insight into why this is the case?

Thanks,

Alex

Title: Re: ADC Verilog-A Model Symbol View
Post by Frank Wiedmann on Apr 29^th, 2020, 2:40am

I suggest that you take a look at https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000911FBUAY and https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000911TpUAI.

Title: Re: ADC Verilog-A Model Symbol View
Post by Ken Kundert on Apr 29^th, 2020, 1:23pm

Spectre is not ADE. The limitation is in ADE not Spectre, and it has always been there. I put the examples in the book without checking that they were compatible with ADE. That was my mistake. Sorry about that.

-Ken