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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> how to probe a net within a hierarchy https://designers-guide.org/forum/YaBB.pl?num=1595988660 Message started by matisse on Jul 28th, 2020, 7:10pm |
Title: how to probe a net within a hierarchy Post by matisse on Jul 28th, 2020, 7:10pm Hello, I am trying to implement something like the deepprobe function that is provided by Cadnece, but with veriloga only, as I use HSPICE. The idea is to be able to probe a net in a sub-block without having to pin that net out to the top level. Right now I have some code like this, but the output just reads some mV and does not track the internal net. Code:
a few questions:
I have consulted the Accellera language reference manual, and have not had any luck. BTW, I have The Designer's Guide to Verilog AMS book, and I find it is very well written. Thanks for that. |
Title: Re: how to probe a net within a hierarchy Post by davidshw on Aug 4th, 2020, 5:46pm as I know Hspice directly support hierarchy node, you can add this statement in the hspice netlist vprobe1 xtb.clk10x_h out 0 |
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