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Design >> Mixed-Signal Design >> Delay Line
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Message started by Cascody on Feb 4^th, 2021, 10:46pm

Title: Delay Line
Post by Cascody on Feb 4^th, 2021, 10:46pm

I have to delay a digital pulse by 30ns with an accuracy of ~1ps. Can this be achieved using the inverter chain delay line? If not, please suggest a topology. I couldn't find much literature on this.

I am using TSMC 65nm process.

Title: Re: Delay Line
Post by Horror Vacui on Jun 28^th, 2021, 1:13am

What is accuracy? It seems an impossible mission in the light of process variations and local mismatches.

Though if you need a delay line with 1ps resolution, which will be calibrated to a reference, then sure it is possible. The delay can be in multiple ways even in the simplest CMOS inverter. The delay is sensitive to the supply voltage, backgate voltages of the transistors, current starving can be used, etc.