The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Element for producing half and one clock cycle delay in Cadence https://designers-guide.org/forum/YaBB.pl?num=1644930214 Message started by D-Generation X on Feb 15th, 2022, 5:03am

 Title: Element for producing half and one clock cycle delay in Cadence Post by D-Generation X on Feb 15th, 2022, 5:03am Hi All,I want to introduce a delay of half and one clock period in an analog circuit. I need an element/circuit that can produce half-clock period in real circuit to be taped out. I cannot use a D flip flop as the output needed is an amplitude varying square signal. (atch 2). Looking forward to ideas..

 Title: Re: Element for producing half and one clock cycle delay in Cadence Post by polyam on Mar 8th, 2022, 9:28am Hi, Perhaps you could use the clock/shifted version of that in an analog fashion, something like summing amplifier, to create different levels and to sum them. I highly doubt you could use logics to create such a function because the logic level is always gnd/VDD. Simply treat the clock as if it is an analog signal.

 Title: Re: Element for producing half and one clock cycle delay in Cadence Post by D-Generation X on Mar 10th, 2022, 2:21am Sorry, I was not able to get your point. I will post a better diagram from simulink, please have a look

 Title: Re: Element for producing half and one clock cycle delay in Cadence Post by polyam on Mar 10th, 2022, 10:34am It is a bit difficult to open a brainstorming discussion without knowing enough details. I am assuming that you are generating such a clock, or better said a waveform, with analog circuits. Is my assumption correct? How are you going to generate such a waveform? My initial thought is that you cannot generate that clock with logics. Can you? I haven't given so much thought to this problem but I see your waveform as a pure analog signal with different voltage levels. One solution could be using a simple low pass filter i.e. 1/1+sTs. Playing with time constant you can make a variable delay. However, there are two issues here, first you are eliminating higher order harmonics by doing so. Also, the output of the filter has to settle fast enough in order not to have distortion. Perhaps, you could approach the problem with an all pass filter and having control on the delay of analog all pass filter but settling time is still a big of concern. I would be nice if you could give a little bit of background on this problem. The application, how you want to generate that waveform etc.

 Title: Re: Element for producing half and one clock cycle delay in Cadence Post by D-Generation X on Mar 11th, 2022, 2:43am Hi Polyam,Yes you are right, lets just call it as a analog square waveform. So I am actually designing a compensation circuit, and this waveform is the compensation signal which is to be delayed by half clock period and added for compensation.This waveform is exactly as shown in previous figure, it has fixed frequency, fixed period(100%) but varying amplitude. Just so not be confused with clock signal. Its a pure analog signal with different voltage levels hence I need an analog delay here. Logic gates wont work here.Since these voltage levels are very low , it is important that amplitude are not affected. Meanwhile, I will check about all pass filters...

 Title: Re: Element for producing half and one clock cycle delay in Cadence Post by polyam on Mar 11th, 2022, 6:14am Watch this specifically 15:25https://www.youtube.com/watch?v=R8GR8o7DEbEand https://www.circuitstoday.com/all-pass-filtersThat's one way of implementation

 Title: Re: Element for producing half and one clock cycle delay in Cadence Post by D-Generation X on Mar 15th, 2022, 5:53am I will check, thanks.But do you think there is a way using a variation of switched capacitor circuits?