The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Spectre cmin setting https://designers-guide.org/forum/YaBB.pl?num=1658946303 Message started by bmurmann on Jul 27th, 2022, 11:25am

 Title: Spectre cmin setting Post by bmurmann on Jul 27th, 2022, 11:25am I am simulating a high-fidelity SC circuit and I am seeing some unexpected behavior with the Spectre cmin setting. The designers I work with tend to use a default of cmin=10f as some reasonable floor for node capacitance to ground, but when I simulate with that setting it seems that some critical nodes start violating charge conservation (with errors being a couple of tens of uV on caps around 1p).I may be misunderstanding what cmin exactly does, but I thought it literally just adds shut caps to ground at every node. In my circuit, there are already caps much larger than 10f to ground at every node yet setting cmin=10f has a strong effect on the simulation error. I am quite puzzled by this and the only thing I could think of is that the added cmin caps are not properly accounted for as the simulator works on conserving charge?

 Title: Re: Spectre cmin setting Post by Ken Kundert on Jul 27th, 2022, 12:44pm It's been 30 years, so my memory might not be terribly reliable, but as I remember it the cmin capacitors were implemented without error control.  Meaning that the cmin capacitors should act as normal capacitors except that the time step will not be reduced to accurately resolve the capacitor currents during fast transients.  The logic behind that decision stems from the belief that cmin is a convergence parameter rather than a modeling parameter.  In other words, there is no reason to believe that in a real circuit each node would have an equal amount of capacitance to ground, so adding cmin to model the circuit is not really useful.  Instead, adding a small capacitor to ground at every node results in smoothed waveforms that can improve convergence.  Since cmin is a convergence parameter rather than a modeling parameter, we assumed that cmin would be set to a value that is much smaller than the actual capacitors in the circuit.  In other words, cmin is intended to be set to a value that would be considered negligible.If the value is negligible, why specify it?  The default move of a simulator when it gets into convergence trouble during a transient analysis is to shrink the time step.  If the waveforms are smooth, shrinking the time step results in the solution at the previous time step being a better starting point for the Newton iteration at the current time point.  It should always be possible to shrink the time step enough so that the previous solution is within the region of convergence for the current point.  This logic breaks down if the circuit exhibits jumps (discontinuous changes in the solution trajectory).  Adding a small capacitor from every node to ground should smooth those jumps, allowing the shrink-the-time-step strategy to continue to work.  And it does not matter if the cmin value is negligible, because the simulator can always choose a time step small enough for the smoothing to work its magic.So, fundamentally, using cmin to model actual circuit parasitics violates the assumptions we made when implementing the feature.  That is not necessarily a problem, just something you should be aware of.  That, and the fact that the simulator it not doing its normal error control on those capacitor voltages.However having said all that, I cannot see how cmin capacitors can result in charge conservation issues.  As far as I know, there are only two things that can result in violating charge conservation:1. incremental models2. Newton residueIncremental models are nonlinear models formulated using derivatives of fundamental quantities (R, G, C, L) rather than fundamental quantities themselves (V, I, Q, φ).  The early SPICE MOS models (MOS2, MOS3) were formulated using capacitance rather than charge and so suffered terrible charge conservation issues.  The modern MOS models are now all formulated using charge, and so this issue is much less of a problem.  However, foundries will often supplement the standard MOS models with added nonlinear elements implemented in Verilog-A, and those models are sometimes problematic because they are formulated using capacitance rather than charge.Newton residue is the amount by which the circuit equations are allowed to be violated.  Newton's method is an iterative approach that starts with a guess at the final solution that is refined on each iteration.  In order for Newton's method to be practical, that iteration must be terminated before the final solution is reached, which would otherwise take an infinite number of iterations.  The computed result will differ from the true solution by a small amount, and that amount is the residue.  SPICE formulates the circuit equations using KCL, and so the residue equals the amount by which KCL is not satisfied.  So it represents the amount of charge that is created or destroyed at each time point.In general the Newton residue is a much smaller contributor to charge conservation errors than incremental models, but incremental models are rare whereas Newton residue is created at every time point whenever the circuit is nonlinear.In the case of incremental models and Newton residue, charge conservation is only corrupted if the model is nonlinear.  In the case of incremental models, it is the changing capacitance that is the genesis of the error in the charge, and in linear models the capacitance does not change.  In a Newton iteration, a linear circuit the solution is computed exactly on the first iteration, meaning that the iteration can be terminated without error.  Thus, I am not seeing a way for cmin to contribute to charge conservation error.⟪ continued in next post ⟫