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Design Languages >> Verilog-AMS >> Assignment timing defined by timer event
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Message started by sjwprc on Aug 7^th, 2022, 3:06am

Title: Assignment timing defined by timer event
Post by sjwprc on Aug 7^th, 2022, 3:06am

In the verilogA, i define a integer N, which is set to 0 at 25ms by timer(25), in the transient, i notice the waveform is shown as attachment. There is obvious drop procedure. Although N = 0 at 25ms, but it starts to drop from ~ 24.5ms, is there anyway to avoid such behavior?
I have tried to use different errpreset, it can be improved by conservative, but still not good enough.
Welcome to your comment.

Title: Re: Assignment timing defined by timer event
Post by Ken Kundert on Aug 9^th, 2022, 10:54pm

If you want help, you should give the model.

Title: Re: Assignment timing defined by timer event
Post by Ken Kundert on Aug 10^th, 2022, 8:00pm

I recommend you read Functional Modeling. It explains many of the things you must do to get an accurate, robust, and efficient abstract model of a circuit.

-Ken