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Design Languages >> Verilog-AMS >> Frequency Measurement when clock is constant (wreal)
https://designers-guide.org/forum/YaBB.pl?num=1663686181

Message started by amsrc on Sep 20^th, 2022, 8:03am

Title: Frequency Measurement when clock is constant (wreal)
Post by amsrc on Sep 20^th, 2022, 8:03am

Hello All,

there is a similar thread covering this, but using veriloga/verilogams: https://designers-guide.org/forum/YaBB.pl?num=1629723383

Now I would like to implement the same but using wreal only (or systemVerilog) i.e. I cannot use the @timer function.

If the clock doesn't toggle then the frequency should become zero after a duration that is longer than the period of the lowest frequency that is expected.

What is the best way to implement this?

I am using the code below as a starting point. Thank you very much!

// MEASURE ACTUAL DIGITAL FREQUENCY:
real fdig,tupd=0;

// on leading clock edge
always @(VCO_OUT) begin
// compute F=1/period (Hz)
if (tupd>0) fdig=1e9/(($realtime-tupd)*2);
tupd = $realtime; // and save edge time
end

Title: Re: Frequency Measurement when clock is constant (wreal)
Post by amsrc on Sep 20^th, 2022, 8:10am

Please see attached picture.

Title: Re: Frequency Measurement when clock is constant (wreal)
Post by Ken Kundert on Sep 20^th, 2022, 9:22am

Here is how I have implemented this idea in Verilog-AMS.
//determine frequency of output

Code:

always @(posedge out) begin
t = $abstime;
freq = 1.0/(t – prev);
prev = t;
disable oscDead;
end

// if no crossing for a while, assume oscillator is dead
always begin : oscDead
#(100n) freq = 0;
end

Notice that the first always block triggers on posedge out. You don't have the posedge, so you are measuring the half-period rather than a full period. You approach will not work well on non-symmetric waveforms.

-Ken

Title: Re: Frequency Measurement when clock is constant (wreal)
Post by amsrc on Sep 26^th, 2022, 8:57am

Thank you very much for your answer Ken!

You are right when you say that the approach using

always @(VCO_OUT) begin

will not work well on non-symmetric waveforms. This approach assumes a 50% duty cycle which is not necessarily the case.

Therefore I followed your suggestion of using the posedge.

I tried implementing your approach and it is working almost fine.

The real variable "freq" becomes 0.0 when we have a period longer than e.g. 40ns.

The only problem is that as soon as VCO_OUT goes high again the frequency will be re-calculated immediately with the values of variables "t" and "prev" because these values were not "reseted". See picture below.

Title: Re: Frequency Measurement when clock is constant (wreal)
Post by amsrc on Sep 26^th, 2022, 9:01am

To solve the issue mentioned in the previous reply the variable "prev" was also "reseted" to 0.0.
Additionaly the freq is calculated only if "prev" is greater than 0.0.
With this modification I am getting the expected results. See picture below.

Again, thank you very much for your help. I see now how disabling the block implements what the @timer function was doing in veriloga.