The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Workaround for using systemVerilog type #delay
https://designers-guide.org/forum/YaBB.pl?num=1669828397

Message started by mikev on Nov 30^th, 2022, 9:13am

Title: Workaround for using systemVerilog type #delay
Post by mikev on Nov 30^th, 2022, 9:13am

Is there a work around for using systemVerilog type delays in veriloga-ams?

For example, in sv:
#1us
#1ms
#1ns

Is there a way to do this in vams?

Thanks in advance.

Title: Re: Workaround for using systemVerilog type #delay
Post by Ken Kundert on Nov 30^th, 2022, 11:34am

Set the time unit in the `timescale directive to 1s, then use the scale factor without the units. For example:

Code:

`timescale 1s/1ps

...

always #50n out = !out;