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Analog Verification >> Analog Functional Verification >> How to create a verilog-A testbench to run a sweep of all input pins
https://designers-guide.org/forum/YaBB.pl?num=1691027150

Message started by avlsi on Aug 2^nd, 2023, 6:45pm

Title: How to create a verilog-A testbench to run a sweep of all input pins
Post by avlsi on Aug 2^nd, 2023, 6:45pm

Hi,
I am trying to use verilogA to run functional verification of some sub blocks.

I have created the schematic in such a way that there are 2 symbols
1. DUT - Device Under Test
2. STIM - Stimulus - This contains DUT input pins as output pins and vice versa

I have a bi directional IO to verify in the DUT. I am currently settling each pin voltage as a test case and verifying whether the operation makes sense. I want to do a single testcase without any sweep variables using verilogA to run through combinations and verify the output according to datasheet of the IO for both input and output mode.

Can anyone share a example on how to get it done.

Title: Re: How to create a verilog-A testbench to run a sweep of all input pins
Post by Ken Kundert on Aug 3^rd, 2023, 5:48pm

Can you use Verilog-AMS? It is much better suited for the task.

Title: Re: How to create a verilog-A testbench to run a sweep of all input pins
Post by avlsi on Aug 3^rd, 2023, 6:36pm

Hi Ken,
I am using spectre as simulator. I am not sure whether it supports verilog ams.

Title: Re: How to create a verilog-A testbench to run a sweep of all input pins
Post by Ken Kundert on Aug 3^rd, 2023, 11:27pm

It does not. You would need AMS Designer.

Title: Re: How to create a verilog-A testbench to run a sweep of all input pins
Post by avlsi on Aug 4^th, 2023, 1:12am

Thanks Ken. I might have limited access to AMS designer. Is there any example to do this verification there?

Title: Re: How to create a verilog-A testbench to run a sweep of all input pins
Post by Ken Kundert on Aug 5^th, 2023, 12:42pm

You can find a conceptual description of the process along with a somewhat incomplete example here: Introduction to Analog Verification.

Title: Re: How to create a verilog-A testbench to run a sweep of all input pins
Post by avlsi on Aug 16^th, 2023, 4:52am

Hi Ken,
I could try sweeping the pins in the vlogams. I had to do some custom blocks to do d2a and a2d conversions at the boundaries.

for(i=3'b000; i<=3'b111; i=i+1'b1)
begin
a = i[2] ;
b = i[1];
c = i[0] ;
// Print the values (for simulation visibility)
$display("i = %b, a = %b, b = %b, c = %b", i, a, b, c);
#(10000); // Wait for so much time steps
end

one thing I am concerned, whether I am doing overkill by sweeping inputs and running a digital simulator instead of analogue simulator for block-level checks.

Is there a better way to use Verilog-A with this #(10000) to sweep input?

Title: Re: How to create a verilog-A testbench to run a sweep of all input pins
Post by Ken Kundert on Aug 21^st, 2023, 11:43pm

Verilog-AMS is a good skill to have. And the ability to write testbenches in Verilog-AMS is a particularly useful aspect of that. I suggest that you think of learning and using Verilog-AMS as an investment.

You can write testbenches in Verilog-A but it is ugly and nobody that knows Verilog-AMS would do so. Since it is unpopular, I cannot point you to any examples that you could learn from. There are some things on functional modeling in Verilog-AMS, which is helpful but not the whole story (Functional modeling in Verilog-A).