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Simulators >> RF Simulators >> sample vs continuous phase
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Message started by tempora123 on Sep 6^th, 2023, 5:50am

Title: sample vs continuous phase
Post by tempora123 on Sep 6^th, 2023, 5:50am

hi,

quick question about sampled vs continuous time system phase.

when using sampled system (here dc/dc converter) there is an additional delay td of e^-jwtd in the loop due to sampling. Therefore, my expectation (and excel's) was to have a difference in phase in Bode plots when approaching the sampling frequency. However, pss + pac shows somehow different results. Attached spectre's sim results and excel calculations.

It seems pss+pac phase results start rolling off much closer to the sampling frequency than e^-jwtd predicts.

Does anyone know why it is so?

Title: Re: sample vs continuous phase
Post by Ken Kundert on Sep 7^th, 2023, 11:46pm

e^-jwtd is the delay of an ideal delay line. What you have is a sampled data system. Its delay will have a sin(x)/x characteristic.

Title: Re: sample vs continuous phase
Post by tempora123 on Sep 8^th, 2023, 1:54am

Thank you Ken for the reply. I'll double check and come back in case of additional questions.

Best regards

Title: Re: sample vs continuous phase
Post by tempora123 on Sep 11^th, 2023, 9:17am

Hi Ken,

I have one additional question. Since the DC/DC power stage signal flow is from switches' gates to drains, will we still see the sinc(x) behaviour there?

I agree that the sampled nature of the signal will be seen from VDD/VSS (e.g. sources) to VOUT (drains).

I've tried simulating the power stage (high side only) as sample and hold but the input signal being at the gate of the switch, instead of source, but I get completely wrong results.

Thank you for clarifications.

Title: Re: sample vs continuous phase
Post by Ken Kundert on Sep 11^th, 2023, 8:14pm

I cannot make any sense of your question. Are you thinking the output switch is the only sampling process in a DC/DC converter. What about the PWM?

Title: Re: sample vs continuous phase
Post by tempora123 on Sep 12^th, 2023, 12:16am

hi Ken,

as a starting point I have tried a simple voltage control loop, like for example here:
https://www.researchgate.net/figure/Voltage-Mode-Controlled-Buck-dc-dc-Converter_fig1_281992799

analysing the phase shift across different stages.

Do you suggest to look into phase shift from Vcon to switch's output rather than from PWM signal to its output?

Title: Re: sample vs continuous phase
Post by Ken Kundert on Sep 12^th, 2023, 12:32am

I am confused as to why are asking me. Why would I have an opinion on what signals you should be looking at?

Title: Re: sample vs continuous phase
Post by tempora123 on Sep 12^th, 2023, 1:24am

ok, I don't see the sinc(x) behaviour at the switch stage, other blocks (LC filter and errAmp with compensation network around it) are continuous time and their H(s) are as expected.

Title: Re: sample vs continuous phase
Post by Ken Kundert on Sep 14^th, 2023, 3:40am

I hope you understand that you won't see a perfect sin(x)/x as the sampling processes in a switching converter are not ideal sample & hold processes. Instead they will have sin(x)/x characteristics.

Both the PWM and the switch & filter are blocks that exhibit both sampling and memory, and so I would expect to contribute sin(x)/x like characteristics.

The whole thing is a loop, so I would expect to see sin(x)/x characteristics pretty much everywhere.

I'm afraid you are going have to figure out what is going on on your own. I have very limited information and so can only guide you with generalities ad I feel like I have pretty much done all I can.

I encourage you to try to understand what you are seeing. It is my experience that SpectreRF results can be challenging to interpret, but can provide insight if you take the time to understand them.

-Ken

Title: Re: sample vs continuous phase
Post by tempora123 on Sep 14^th, 2023, 11:17pm

Thanks for the feedback. I can see that the sinc behaviour is present due to sampling. but maybe you can clarify why it is present when input is DC? In the pic attached, let's skip Q2, VIN=DC, Q1 is clocked.

Thank you

Title: Re: sample vs continuous phase
Post by Ken Kundert on Sep 15^th, 2023, 11:06am

Presumably you performed a PAC analysis to see the sin(x)/x behavior. So your input is not DC. It is a sinusoid swept over a wide range of frequencies. The sampiing comes from the clock on q1. The voltage on the capacitor will be a sampled-and-held version of the input. It won't be a simple sin(x)/x because of the influence of inductor and imperfections in the switch.

Title: Re: sample vs continuous phase
Post by tempora123 on Sep 18^th, 2023, 7:58am

Thank you for the feedback, all is clear now.

Title: Re: sample vs continuous phase
Post by tempora123 on Sep 24^th, 2023, 3:37am

for completeness: I've updated my calculations with the sinc behaviour due to sampling. Now, the phase rolls off much closer to fs frequency as per attached pic.