The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Analog Verification >> Analog Functional Verification >> VerilogA random DC value
https://designers-guide.org/forum/YaBB.pl?num=1694181814

Message started by Horror Vacui on Sep 8^th, 2023, 7:03am

Title: VerilogA random DC value
Post by Horror Vacui on Sep 8^th, 2023, 7:03am

Is there any way to generate random values with VerilogA for a SPECTRE's DC analysis?
The $random function is evaluated at every timestep. It gives a good random number during a transient analysis, but its values for DC and t=0 in transient is always the same.

In general I am curious whether something like is possible to achieve with VerilogA, because it was a surprise to me, that I found no solution.

Title: Re: VerilogA random DC value
Post by Ken Kundert on Sep 9^th, 2023, 12:24am

There are various ways to run a statement only once. There is the "analog initial" block or "@(initial_step)". Just use a random function such that it gets called once, save it to a variable, and then use that variable to drive the output.

Title: Re: VerilogA random DC value
Post by Horror Vacui on Sep 11^th, 2023, 4:26am

I do not know which random function could I use. The random functions in VerilogA require a seed. Generating a random seed will have the same problem as I already have.

I've looked in different ways as well, but to no avail:
I haven't found a way to call a system function. I tried using the $simparam("systime") as a seed, but its resolution (1sec) wasn't random at all.
I also have not found (yet) a reliable way in our flow to execute a script between netlisting and simulation to insert a random value.

Therefore I would very grateful for any small working example.

Here is an example of mine:

Code:

`include "discipline.h"
`include "constants.h"

module rand_bit_simple (vout);
output vout;
electrical vout;
parameter integer seed = 21;
integer var_seed;
integer rnd;

analog begin
@ (initial_step) begin
var_seed = seed; // variable is needed; updated after every step
rnd = $random(var_seed);
end // initial step

V(vout) <+ rnd*1e-12;

end //analog
endmodule

Title: Re: VerilogA random DC value
Post by Ken Kundert on Sep 11^th, 2023, 8:02pm

You might try reading a few bytes from /dev/random or /dev/urandom and using that as the initial seed.

You definitely need a transition function around *rnd* in your contribution statement.