Hi all:
   In the following ESD circuit picture, Why add two resister Rp1, Rn1? Can I simplely short it?
    Picture from JSSC VOL. 35, NO. 8, AUGUST 2000 pp.1194;
ESD Protection Design on Analog Pin with Very Low Input Capacitance for High-Frequency or Current-Mode Applications

The comment regarding the dv/dt triggering is correct.
It is very much a function of process technology, but generally, by generating a gate voltage during the initial phase of the ESD event, channel current flows, and this helps to lower the actual trigger threshold (which typically needs to be higher than the reverse breakdown voltage of the drain junction).  The channel current can force the triggering to be lower than this limit and induce an earlier snapback.

The size of the resistor is "supposed" to be sized so as to generate the proper channel charge for ESD events in question.  HBM/MM type events will not generate a lot of coupled voltage to the gate due to the slow risetimes, thus requiring larger resistors, both to allow for coupling as well as to lengthen the time constant on the gate node.  CDM type events, with fast rise times will generate larger coupled voltages to the gate, in shorter time periods, and thus require smaller resistors.
You have to ask yourself then , by how much can I lower the trigger point for snapback with an applied Vgs on the ESD device (a process related question), and what type of esd events am I most concerned about/targeting (a design/product related question).

thanks all very much!
 Can I simply comprehend those as follow?
 When ESD procedure occur ,The Rp and Rn will product  IR-drop voltage, which serve as Vgs of MOS conducting the MOS channel. Then the MOS channel steers the ESD current  and parallel working with Dp or Dn .

SRF
   Thanks for you patience. Your answer is really a great help to me, althought there is still somthing i am not quite sure about. I am a fresh comer to the area of  High-Speed IO ESD, anyway:).

The trade-off between parasitic capacitance versus ESD performance, and then adding in the arguements of diodes versus SCR/snapback based devices is old and very inconclusive.

It is inconclusive because performance of diodes/SCR's/snapback devices are very much process and design dependent, as is the parasitic capacitance.  Some processes have very good snapback performance for their standrad ggNMOS's, others do not.  Some have very good diode conductance in the high current region, other do not.  Also capacitance is as much dependent on metalization as it is on device type/device design.  There are no clear answers.

I personally subscribe to the idea that diodes can generally deliver the best ESD performance per unit capacitance.  There was also a paper which had a similar conclusions:
"C., Richier, et al., “Investigations of different ESD protection strategies devoted to 3.3V RF applications (2Ghz) in a 0.18um CMOS process,” Proc. EOS/ESD Symp., pp251-259, 2000."

I actually developed a diode for one of my clients that achieved ~60-70mA/fF of performance, under high current conditions.  (it was a ~50fF diode that could sink ~3.5A @ ~5V)
(Note this was a very aggressive diode construction that was uncoventional, you won't find it in your standard 3rd party ESD library, but is evidence of the superiority of diodes--IMHO).
I, personally, have yet to achieve similar performance using an SCR type design (someone else might know of one).  Note I would never even consider ggNMOS or gcNMOS devices for high speed applications, the drain-gate capacitance is a horrible parasitic that offers you nothing.

If you find that your diodes are excesively loading down your circuits, I would first look at your diode layouts and find ways to optimize it.
You may also need to look at your product's/SoC's ESD and IO architecture, to find ways of minimizing ESD burden on your sensitive pins.  There are many techniques to accomplish this.