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latch up failure due to design ? (Read 3758 times)

jason_class

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Posts: 39
singapore

latch up failure due to design ?
Oct 05^th, 2006, 9:18am

Dear All

I need some help to understand more about latch up failure.
Usually, latch up failure happens are due to improper layout of design OR due to process issue?

I heard that often latch up failure happens in IO mos. What are they for? Why it is often the case latch up happens at IO mos? Is the W/L bigger than normal logic mos or some other reason?

If anyone has any good reference on this topic, kindly share with me.

Thank you for your help.

best rgds
Jason

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loose-electron

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Posts: 1638
San Diego California

Re: latch up failure due to design ?
Reply #1 - Oct 6^th, 2006, 3:33pm

most latch problems are due to poor layoutsw without sufficient substrate contacts or well tie ups.

I/O cells are more prevalemt to the problem due to the higher currents in the circuits

http://www.fairchildsemi.com/an/AN/AN-600.pdf#search=%22%22latch%20up%22%22

See the above - it is all about keeping the IR low enough so that you do not turn on the transistors (getting Vbe over 0.6 or there abouts)

Jerry

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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jason_class Community Member Offline Posts: 39 singapore	Re: latch up failure due to design ? Reply #2 - Oct 20^th, 2006, 11:55pm Dear Loose e- Good link to share. Checking it out and will be back for more... Jason
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