Geoffrey_Coram
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Per the new Verilog-AMS LRM, you can define output variables with attributes,
If you have a variable called "iavl" that is used to store the avalanche current, declare it at top level (module scope, not in a named block) with
(* desc="avalanche current" *) real iavl;
(and, obviously, remove the declaration you had before). I believe HSpice supports this new feature. I forget the exact syntax, though, for requesting that HSpice save it to the .tr0 file; I think it's similar to what you do for saving "gm" from a transistor.
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