Wow, you guys really have a stubborn streak! Ken was trying to help you, and that document about modeling varactors also gives some hints on bad formulations that can cause convergence problems. Verilog-A is a language for writing what you want for simulation, I don't know what you think it is ...
Anyway, your model needs to be written in terms of charge (see the document for why!), and would look like this:
Code:`include "discipline.h"
module timmy(t, b);
inout t, b;
electrical t,b;
parameter real C0 = 1p from (0:inf);
real charge;
analog begin
charge = 2 * C0 * sqrt(V(t,b));
I(t, b) <+ ddt( charge );
end
endmodule
Note that capacitance (for a (nonlinear) capacitor is dQ/dV, so this model has the dependence you asked for.
Wasn't that simple?