thomasross20
Junior Member
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Posts: 30
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Hello,
I'm trying to find a way of simulating the INL/DNL of a fully-differential pipeline ADC in Cadence, using spectre/verilog-A. There is an ahdl library with DNL/INL blocks, but these are single-ended and their operation not explained well. Any help on this matter would be appreciated. Note the pipeline has a delay time before it starts outputting correct data..
Secondly, several references are at odds when defining the DNL of an ADC. Is it related to the width of the analog input along the x-axis or the height of the digital transition on the y-axis? I would say the analogue width...
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