jsun
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Posts: 14
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Hi, I am using cadence to do very simple mixed signal simulation. I created 6 shift registers by verilog and gave analog signal as input. Interface elements were successfully inserted. Netlists for analog and digital were created, but while running tran simulation in ADE, I could not get the plot. It stoped as below during the simulation without error message being reported.
Installed compiled interface for single_cpw. Opening directory analog/input.ahdlcmi/ (770) Installed compiled interface for bsource_1.
Notice from spectre during topology check. Only one connection to node `vdd!'.
Circuit inventory: nodes 10 equations 32 iprobe 9 a2d 3 capacitor 6 d2a 6 vsource 4
************************************************ Transient Analysis `tran': time = (0 s -> 10 ns) ************************************************
Here is the output from analog netlist,
// Generated for: spectre // Generated on: Apr 28 14:57:09 2009 // Design library name: SAR_ADC_Layout // Design cell name: top_tb // Design view name: config simulator lang=spectre global 0 vdd! include "~/c130nm/icfspectre.init" // BEGIN Flat Interface Elements // Flattened IE at /net10 uses port path 99999 // Flattened IE at /net5 uses port path 99998 // Flattened IE at /net11 uses port path 99997 // Flattened IE at /net9 uses port path 99996 // Flattened IE at /net7 uses port path 99995 // Flattened IE at /net8 uses port path 99994 // Flattened IE at /net4 uses port path 99993 // Flattened IE at /net6 uses port path 99992 // Flattened IE at /net3 uses port path 99991 // END Flat Interface Elements
// Library name: SAR_ADC_Layout // Cell name: top_tb // View name: schematic // Inherited view list: SimMosfetStandard spectre verilog behavioral //functional hdl system verilogNetlist auCmos_sch cmos_sch cmos.sch //ads_schematic schematic auGate_sch auGate.sch gate_sch gate.sch //extracted PLS_RCMIN_NoRC PLS_RCMIN_FSextract PLS_RCMIN_Mixed //PLS_RCMIN_Cc_RCc PLS_RCMIN_R PLS_RCMIN_C PLS_RCMIN_RC PLS_RCMIN_Cc //PLS_RCMIN_RCc PLS_RCTYP_NoRC PLS_RCTYP_FSextract PLS_RCTYP_Mixed //PLS_RCTYP_Cc_RCc PLS_RCTYP_R PLS_RCTYP_C PLS_RCTYP_RC PLS_RCTYP_Cc //PLS_RCTYP_RCc PLS_RCMAX_NoRC PLS_RCMAX_FSextract PLS_RCMAX_Mixed //PLS_RCMAX_Cc_RCc PLS_RCMAX_R PLS_RCMAX_C PLS_RCMAX_RC PLS_RCMAX_Cc //PLS_RCMAX_RCc PLSimported LPEimported PLS_DSPF_INCLUDE ahdl veriloga C3 (net8 0) capacitor c=1f ic=0 C0 (net11 0) capacitor c=1f ic=0 C5 (net6 0) capacitor c=1f ic=0 C1 (net10 0) capacitor c=1f ic=0 C4 (net7 0) capacitor c=1f ic=0 C2 (net9 0) capacitor c=1f ic=0 V4 (net3 0) vsource type=pulse val0=0.0 val1=1.2 V3 (net5 0) vsource type=pulse val0=0.0 val1=1.2 V2 (net4 0) vsource type=pulse val0=0.0 val1=1.2 V5 (0 0) vsource dc=0 type=dc V0 (vdd! 0) vsource dc=1.2 type=dc // BEGIN Hierarchical Interface Elements _ie99991 (net3 0) MOS_a2d dest="99991" timex=1m vl=0.5 vh=0.7 _ie99992 (net6 0) MOS_d2a src="99992" fall=50p rise=50p val1=1.2 val0=0 _ie99993 (net4 0) MOS_a2d dest="99993" timex=1m vl=0.5 vh=0.7 _ie99994 (net8 0) MOS_d2a src="99994" fall=50p rise=50p val1=1.2 val0=0 _ie99995 (net7 0) MOS_d2a src="99995" fall=50p rise=50p val1=1.2 val0=0 _ie99996 (net9 0) MOS_d2a src="99996" fall=50p rise=50p val1=1.2 val0=0 _ie99997 (net11 0) MOS_d2a src="99997" fall=50p rise=50p val1=1.2 val0=0 _ie99998 (net5 0) MOS_a2d dest="99998" timex=1m vl=0.5 vh=0.7 _ie99999 (net10 0) MOS_d2a src="99999" fall=2n rise=3n val1=1.2 val0=0 // END Hierarchical Interface Elements simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \ sensfile="../psf/sens.output" checklimitdest=psf tran tran stop=10n errpreset=liberal ic=node cmin=1f write="spectre.ic" \ writefinal="spectre.fc" annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile saveOptions options save=all pwr=all currents=all
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