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view in cadence mixed signal simulation (Read 5844 times)
depend135
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view in cadence mixed signal simulation
Apr 21st, 2009, 12:27am
 
I am using cadence spectreverilog simulator to do the mixed signal simulation.But i am confused when it comes to typing the view name of my digital module which is discriped by verilog.
some materials say that it should be "functional",some say "behavioral",is there any difference between them?
Are there any cadence help documents talking about the concept of View in Cadence?
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Andrew Beckett
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Re: view in cadence mixed signal simulation
Reply #1 - Apr 24th, 2009, 6:49am
 
Views are different representations of a design. The actual names of the views are not that important, provided that the netlisters (or elaborator in the case of AMS) knows how to switch into them - and this is controlled either by a switch-list/stop-list or by a config view (created by the hierarchy editor).

As a result, the view names "behavioral" and "functional" are purely arbitrary and just convention. "behavioral" implies you're describing the behavior without necessarily regard to how it would be implemented, and "functional" is closer to the implementation, I guess. But it really doesn't matter - you can put any type of verilog code in the views - although if you're using the very old SpectreVerilog approach you are limited to just what VerilogXL supports (which is a rather old flavour of Verilog).

AMS Designer is the newer mixed-signal simulator from Cadence, and is a single-executable simulator that supports all the languages that the Incisive platform does, as well as VerilogAMS, VHDL AMS, VerilogA, and spectre netlists - so you can have true mixed-signal models, rather than being restricted to pure digital or pure analog models (this is a very short, one-line, description of the differences between SpectreVerilog and AMS!).

Regards,

Andrew.
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jsun
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Re: view in cadence mixed signal simulation
Reply #2 - May 1st, 2009, 3:23pm
 
Hi Andrew,

Does it mean that I just need to create verilog-ams file instead of creating verilog file for digital circuit and veriloga file for analog?

Thanks,
JSun
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makelo
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Re: view in cadence mixed signal simulation
Reply #3 - May 4th, 2009, 4:19pm
 
If you already have a verilog-hdl representation you don't need to create a verilog-ams specific view.  You can simply use the .v file you have with a verilog, functional, or behavioral view type.  These will work fine in the AMS designer simulator.
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