RobG
|
Actually I'm just using a pmos transistor since I'm not up to making a nmos over nwell cap. The rules are incredibly screwed up in this process and I have no time....
OK, that is what I thought. I just wanted to make sure it wasn't some funny physics... I was raised a bipolar man...
I just want to confirm.
Say you had a W=10, L=10 transistor with Cgs=10fF/um^2. Nwell sheet resistance is 1k-ohm/sq. The total cap would be 1pF and Res=1k. So a first order model would be three pmos (1/3pF) and two 500 ohm resistors (RC lumped element). The gates tied to vdd (ignoring poly R) and the sources would be distributed between the 500 ohm resistors: One going to the middle and the other two going to the ends which would be tied to vss.
|