It is still not clear what you want to do. It is possible to build a phase-domain model of your PLL and simulate in any simulator that has a reasonable modeling language, including any circuit simulator that implements Verilog-A. You could also use tools like Matlab. Or you can code the model up your self in any programming language, such as Python or C. However, this is a simplified model; very simplified as you will come to understand when you go to build the models of the various components. This process is described in some depth in
http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf.
Alternatively, you might be looking to do a transistor-level simulation and extract the transfer function. That is possible with RF simulators such as SpectreRF. Basically, you set up the PSS analysis so that its initial transient interval (set by tstab) is long enough to take the PLL into lock, then it computes the periodic steady-state solution. For this to be possible your PLL must satisfy a few criteria. First, it must have a periodic steady-state solution; so your PLL must have no deadzone or fractional-N architectures. And it must be practical to compute the steady-state solution, and so if there is a divider in the loop, its divide ratio must be relatively small. Once you have the steady-state solution, you can run any of the small-signal analyses that work with PSS. Those include PAC, PXF, PSTB, and of course, PNoise. They perform the AC, transfer function, stability, and noise analyses respectively.
-Ken