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Folded cascode compensation (Read 10540 times)
extremis
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Folded cascode compensation
Feb 17th, 2011, 9:02am
 
What is the best way to compensate the folded cascode? I am getting very low phase margin, or even negative.
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Rakesh
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Re: Folded cascode compensation
Reply #1 - Feb 17th, 2011, 9:13am
 
Usually folded cascode is not compensated as the second dominant  (at the folding node ) comes at higher frequency. May be in your design you would have choosen the sizes of the transistors at folding node big. Or increase the gm of the cascode transistor at the folding node.
If this doesnot work out connect a RC between the folding node and ground. This will introduce a zero so that your phase margin will be good..
Is this fine
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wave
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Re: Folded cascode compensation
Reply #2 - Feb 17th, 2011, 11:49am
 
I agree with the previous post.  Ignoring parasitics, a folded cascode is a one pole system.

You do not show the output Cload nor the way you are simulating stability.

Also, I'd look hard at your biasing.  
The P7-N4 leg gives me a headache staring at it.
Specifically, the cascode gates are biased by the signal point of opposite polarity.  Check your PSRR.

Good luck,
WAVE   Cheesy
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subgold
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Re: Folded cascode compensation
Reply #3 - Feb 18th, 2011, 1:11am
 
i am afraid your folded branch has way too little current compared with that of the main input pair, which means your parasitic nondominant poles are quite close to the dominant pole. that results in the small phase margin.

i guess you will also face a transient problem as you dont have enough sourcing current to the load. if u meant to design a rail-to-rail input, then the current summation in the folded branch is likely wrongly constructed.
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Lex
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Re: Folded cascode compensation
Reply #4 - Feb 18th, 2011, 1:26am
 
I think your bias circuit needs an overhaul.
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extremis
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Re: Folded cascode compensation
Reply #5 - Feb 18th, 2011, 3:18am
 
The folded branch has so little current in order to increase the gain (>80dB). The OPAMP should have PM>50 without any load. Maybe i should add a common source stage with Miller compensation.
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sheldon
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Re: Folded cascode compensation
Reply #6 - Feb 18th, 2011, 6:00am
 
Extremis,


1) The input stage is not biased properly

 Starting at the beginning, the current  mirror ratio for N11-N7
is 10uA:320nA. The issue appears that the n-channel input diff
pair includes 2 Vt drops (1V+0.5V) from the source follower
and the input device. So the n-channel current source is not
in saturation, Vds=310uV. Compare the n-channel input bias
current to the p-channel input bias current, 320nA:160uA.  

You may want to either re-consider the source follower or use
larger devices, less gate overdrive, on a 3V supply you cannot
afford Vgs of 1V (N10, N12) for the source follower.

2) You need a folded cascode

  You chose to implement a rail to rail input stage, n-channel
and p-channel connected in parallel. This approach conflicts
with the gain portion of the design. That is, you have a single-
ended output so you need to have a current mirror as the load.
Yet you are trying to fold using p-channel/n-channel mirrors.
This won't work. Folding stages are differential.

Or you have stacked two mirrors, one n-channel and one p-channel,
then driven the mirrors differentially. This is not a folded cascode.

Some options:
1) Give up on the cascode
   Throw away the current of N6 and P1, short them to the
   supplies and connect the mirrors as cascoded mirrors.
2) Implement a real cascode
   Delete the n-channel input and follower, create an actual
   folding stage with the channels: N0, N1, N3, N4.

                                                 Best Regards,

                                                      Sheldon    
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RobG
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Re: Folded cascode compensation
Reply #7 - Feb 22nd, 2011, 11:50am
 
In addition, the N-Channel Diff pair is also not cascoded to it probably kills your DC gain, although since it has no current in it maybe it won't... on the other hand, the low current will set up a pole...

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Nandish Mehta
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Re: Folded cascode compensation
Reply #8 - Feb 22nd, 2011, 9:11pm
 
Adding further, as the low current in the NMOS & PMOS sources at the folding node will also limit the amount of input swing that you can support.

This is because the differential input multiplied by input gm is the current swing that is required to be supported before the active loads go out of the current.

In other words you are achieving >80 db gain because there is no current in the active loads so effective gds is very high.

Regards
Nandish
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