Hi all,
Iam working on macromodeling of sigma delta adc for this i require veriloga model of fully differential opamp (non-ideal) . Its not that iam asking some one to provide me the code.I have written the code with certain specifications (gain=63db,dominant pole at 172khz) but i don't know how to check the correctness of the code(testbench).I want to know if the code i wrote works as desired(i.e., on simulation it gives same gain and dominant pole freq).
The ieee paper that followed to develop this veriloga model can be found in attachment(veriloga code is written for the ckt diagram in the paper) also iam uploading the code i wrote so that you can find mistakes if any.
To the moderator : This is my first post on DG had i voilated any rules by posting anything that i shouldn't have pls remove it and let me know about the same.
Thanks--
Fuzail.
VerilogA code of fully differntial opamp :
`include "discipline.h"
`include "constants.h"
// model opamp - Non Ideal OpAmp Model
module opamp (voutp,voutn, vin_p, vin_n, vspply_p, vspply_n, vcm );
input vin_p , vin_n , vcm;
inout vspply_p, vspply_n;
output voutp,voutn ;
electrical vin_p, vin_n, voutp, voutn, vspply_p, vspply_n, vcm;
parameter real gain = 1412.5 exclude 0.0;
parameter real pole_freq = 172k;
parameter real rin = 12.0M exclude 0.0;
parameter real rout = 75.0;
parameter real ibias = 0.0n;
parameter real vin_offset = 0.0u;
// parameter real slewp = 20.0M from (0:inf);
// parameter real slewn = -20.0M from (-inf:0);
real c1, r1;
real r_rout,gm_nom, vin_val;
electrical coutp, coutn, vref;
analog
begin
@(initial_step)// or initial_step("dc", "ac", "tran", "xf"))
begin
gm_nom = 1.0;
r1 = gain/gm_nom;
c1 = gm_nom/(`M_TWO_PI * pole_freq * gain);
r_rout = rout;
end
vin_val= V(vin_p, vin_n) + vin_offset;
// ------ Vref is at Virtual Ground
V(vref,vspply_n) <+ 0.5*V(vspply_p,vspply_n);
// ------ Input Stage
I(vin_p, vin_n) <+ vin_val / rin;
I(vref, vin_p) <+ ibias;
I(vref, vin_n) <+ ibias;
// ------ GM stage
I(vcm, coutp) <+ (gm_nom/2)*vin_val ;
I(vcm, coutn) <+ -(gm_nom/2)*vin_val ;
// ------ Dominant Pole.
I(coutp, vcm) <+c1*ddt(V(coutp, vcm));
I(coutp, vcm) <+ V(coutp, vcm)/r1;
I(coutn,vcm) <+ c1*ddt(V(coutn, vcm));
I(coutn, vcm) <+ V(coutn, vcm)/r1;
// ------ Output Stage.
I(vcm, voutp) <+ (V(coutp) - (vcm))/r_rout;
I(voutp, vcm) <+ V(voutp, vcm)/r_rout;
I(vcm, voutn) <+ (V(coutn) - V(vcm))/r_rout;
I(voutn, vcm) <+ V(voutn, vcm)/r_rout;
end
endmodule
Couldn't upload ieee paper as the file is large the link is
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4746344 however iam uploading the fig with which i developed veriloga code