Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Oct 30
th
, 2024, 1:52am
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Design
›
RF Design
› Second Order Passive Loop Filter for PLL
‹
Previous topic
|
Next topic
›
Pages: 1
Second Order Passive Loop Filter for PLL (Read 5443 times)
cheap_salary
Senior Member
Offline
Posts: 162
Second Order Passive Loop Filter for PLL
Dec 20
th
, 2015, 8:23am
See attached figure, there are two structures as second order passive loop filter for charge pump base PLL.
How should I choose one of them ?
Just from component's value ?
Back to top
Second_Order_Passive_Loop_Filter.png
IP Logged
loose-electron
Senior Fellow
Offline
Best Design Tool =
Capable Designers
Posts: 1638
San Diego California
Re: Second Order Passive Loop Filter for PLL
Reply #1 -
Dec 28
th
, 2015, 4:10pm
Preference (a)
Why?
It gives a single capacitor from the control voltage to the ground, which allows for the best HF filtering of switching noise.
The non ideal nature of the capacitor makes me go in that direction. Two devices in series will have greater parasitic inductance.
If everything is ideal, parasitics are ignored and non ideal charge pump switching is a non issue, then it does not matter.
However the reality is that they are all important.
Back to top
Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
IP Logged
nrk1
Community Member
Offline
Posts: 81
Re: Second Order Passive Loop Filter for PLL
Reply #2 -
Dec 28
th
, 2015, 10:40pm
To have the zero well below the unity loop gain frequency, C2 >> C1 in your first circuit and C1 >> C2 in the second. The values will come out to be about the same. The first one is more common. There is always some capacitor at the output node and it can be absorbed into C1 in the first circuit. Also, it would be better to put C2 below the resistor or somehow ensure that there isn't a lot of parasitic capacitance from the junction of C2 and the resistor which degrades stability.
Back to top
IP Logged
cheap_salary
Senior Member
Offline
Posts: 162
Re: Second Order Passive Loop Filter for PLL
Reply #3 -
Dec 29
th
, 2015, 7:22am
[Example]Kvco=22MHz/V, Icp=5mA, Ndiv=300, fc=10kHz, PM=45deg
T1=2.24e-7
T2=3.84e-5
T3=6.59e-6
Passive Filter-1
C1=0.0385uF
R2=207ohm
C2=0.186uF
C1+C2=0.2245uF
Passive Filter-2
C1=0.224uF
R2=142ohm
C2=0.0465uF
C1+C2=0.2705uF
Passive filter-2 requires large capacitor than Passive filter-1.
And we can not use grounded capacitor in passive filter-2.
So I don't think there is any merit to use passive filter-2.
Neverthless, these two structures are introduced in literature.
See following.
http://edadocs.software.keysight.com/display/ads2011/Open+and+Closed+Loop+Simula...
This ADS example use Passive Filter-1 now.
However Passive Filter-2 was used previously in same example.
See the followings.
http://edadocs.software.keysight.com/display/ads2009/Phase+Noise+Simulation
http://edadocs.software.keysight.com/display/ads2009/PLL+Simulation+of+DECT+Radi...
Here Passive Filter-2 is still used in these.
Back to top
IP Logged
loose-electron
Senior Fellow
Offline
Best Design Tool =
Capable Designers
Posts: 1638
San Diego California
Re: Second Order Passive Loop Filter for PLL
Reply #4 -
Dec 30
th
, 2015, 6:32pm
45 degrees phase margin?
Over process variance that may be a problem.
For a lowest phase margin corner I am good with it.
Back to top
Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
»» RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.