The Designer's Guide® Community website is a place where analog, mixed-signal and RF circuit designers come to learn about simulation, modeling and design. There are a number of very practical papers on simulation and modeling on the Analysis, Modeling, and Theory pages. A collection of useful example models can be found on the Verilog-AMS page. Papers on design methodology can be found on the Design page. And finally, our most popular feature is the Forum, where designers gather to share information about the challenges they face.
The Designer's Guide Community is built around the contributions of its members. Most chose to contribute through discussions on the Forum, but some go so far as to write and contribute either papers or models. So if you have some special knowledge you would like to share, or if some useful and well-written models, please consider submitting them.
Most people make some very serious but also very common mistakes when writing Verilg-A/MS models.
If you write, or intend to write, Verilog-A/MS models you should read our tutorials, which are brief, but filled with useful information.
Doing so will result in models that are more efficient, more accurate, and more robust.
Geoffrey updated his JFET Verilog-A model. He did a general refresh of the model and fixed some flaws. You can find the latest version here.
I often have the need to include schematics and waveforms into documents or presentation, and I have found that trying to use those generated by Cadence's ADE results in figures that are very difficult to see. So I have created two Python programs that can be used for this purpose: svg-schematic and psf-utils. Both generate SVG files that are very easy to read. svg-schematic converts a small Python program into an attractive schematic; and psf-utils can read a Spectre-generated ASCII PSF file and plot the waveforms or convert them to SVG. Documentation can be found here: svg-schematic and psf-utils. To see and example of a document that contains both schematics and waveforms created with these tools, see flicker-noise. Install with:
pip install --user svg-schematic psf-utils
I have created a new Python package for generating RLC charts. RLC charts are like normal log-log impedance versus frequency charts, except they also include capacitance and inductance grids. RLC charts can very helpful when trying to build linear two terminal models of resistors, capacitors, and inductors. They allow you to read the component and the parasitics values directly from the graph. Documentation can be found at GitHub. Install with:
pip install --user rlc_chart
If you are new to Verilog-A, or are confused by contribution statements, you should read Introduction to Verilog-A. It is a basic introduction to Verilog-A that focuses on how to build branch relationships using the contribution statements. It has been around for quite a while, but it seems relatively unknown.
A paper on writing flicker noise models that are compatible with RF simulation is now available. Flicker Noise Formulations in Compact Models by Geoffrey Coram, et al has been published in IEEE Transactions on CAD, vol. 39, no. 10, October 2020.
Resistor models that demonstrate the problem and the fix are available in a GitHub repository. Also included is a circuit that shows the problem in the BSIM model. The repository includes scripts that allow you to easily run the simulations yourselves.
You should read this article if you are concerned about the accuracy of your RF noise simulations or simply want to understand a little more about flicker noise.