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help on DFF modeling with set and clear (Read 8981 times)
CDR
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help on DFF modeling with set and clear
Jun 25th, 2003, 6:13pm
 
Anybody has the model for D-Flip-flop with set and clear input?
E.g, Set = 0; Q=1;Clr=0;Q=0;

Thanks,

module d_ff_set( vin_d, vclk, vout_q, vout_qbar, clr, set );
input vclk, vin_d,clr,set;
output vout_q, vout_qbar;
electrical vout_q, vout_qbar, vclk, vin_d,clr,set;
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans_clk = 2.5;
parameter real vtrans = 2.5;
parameter real tdel = 3u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);

  integer x;
  integer reset_state;
  analog begin
     @ (cross( V(set) - vtrans, -1 ))
        reset_state = 1;
     @ (cross( V(clr) - vtrans, -1 ))
        reset_state = 0;
     @ (cross( V(vclk) - vtrans_clk, +1 ))
       reset_state =3;
     
     if (reset_state==0) begin
       x =1;
     end
     else if (reset_state==3) begin
       
                   x = (V(vin_d) > vtrans);
       end
    end
        V(vout_q) <+ transition( vlogic_high*x + vlogic_low*!x,
                          tdel, trise, tfall );
        V(vout_qbar) <+ transition( vlogic_high*!x + vlogic_low*x,
                          tdel, trise, tfall );
   end
endmodule
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CDR
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Re: help on DFF modeling with set and clear
Reply #1 - Jun 26th, 2003, 10:38am
 
Could anybody help looking at the model that I had?It doesn't work.
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Geoffrey_Coram
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Re: help on DFF modeling with set and clear
Reply #2 - Jul 14th, 2003, 7:22am
 
CDR -
I'm just glancing at this, haven't tried running it, but I saw what looked like an extra "end" statement -- but now I see that you're missing the "else if (reset_state == 1)" case.

Also, the @cross event does not trigger during the initial condition computation, so you might need to put in some explicit initialization.

Once you fix this, if you still have problems, you should be more specific than "It doesn't work."  Does the simulator complain about syntax? Does it run, but doesn't set or reset?

-Geoffrey
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If at first you do succeed, STOP, raise your standards, and stop wasting your time.
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CDR
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Re: help on DFF modeling with set and clear
Reply #3 - Jul 14th, 2003, 1:49pm
 
Thanks,Geoffrey.

After I add the else if (reset_state==1),also the initial state.The Q output are "high" before the next clock rising edge.If the next clock edge comes,it will follow the data input.How could I keep the data output high,if set==0 while discarding any clock rising edge.
Instead of doing this, I use a mux to select the either "1" or "data input" through the control signal "set",and the set function is syncnorous.By doing this way, I implement the PRBS generator using veriloga.Of course,if anybody can finish set and clr function of a DFF in veriloga,it should be much more helpful.

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Ken Kundert
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Re: help on DFF modeling with set and clear
Reply #4 - Jul 14th, 2003, 2:20pm
 
Try looking at the D flip-flop at http://www.designers-guide.com/Modeling/VerilogAMS/.

-Ken
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Geoffrey_Coram
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Re: help on DFF modeling with set and clear
Reply #5 - Jul 17th, 2003, 8:07am
 
Ken -
The comment above dff2 says that it also lacks set and reset, although a closer inspection shows it has these inputs.

Also, you're mis-using the non-standard above event. The above event is (presently) only in Spectre's Verilog-A, and it does not take a direction argument. If you want to detect negative crossings, you would have to put
if (dir == -1) begin
   @(above(vth - V(clk)))


Since transition doesn't make sense for a dc analysis, I think you should use cross instead of above, and set up a different block of code to handle the dc analysis.

-Geoffrey
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Ken Kundert
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Re: help on DFF modeling with set and clear
Reply #6 - Jul 17th, 2003, 9:54am
 
Ahhh, peer review. I love it!

Okay, I have made the corrections you have suggested.

Thanks,
-Ken
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