Sweep vdd source from 0 to 1.8.
set IC to '0.0'v on the diode-connected BJTs collector nodes. (assuming you are using vertical PNP in N-Well process.)

If you are using Cadence schematic composer and Analog Design
Environmnet ( Analog Artist), you can set up from from GUI.

Actually, you probably also want to try set vdd to 1.8, but use
IC to set the collector voltages to 0.0v so as to force a false
operating points at the beginning of transient to see if the circuit
will settle to the right solution.

If you ramp you VDD from 0, the transient operating points for all
the nodes should all close to 0. You may not be able to find the
start-up problem while there is a real problem.