nano_RF
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Posts: 50
madison
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Hello Ken,
Thanks for your reply first. Two varactor capacitor are used in VCO block of PLL circuit. If i simulate my VCO design seperately by either method (i=dq/dt or cdv/dt) simulation works fine and gives the same result (which i think is correct) ,but when i simulate my whole PLL block where VCO forms a close loop with other block i get fatal error -arithmatic exception. It does'nt say what arithmatic exception.
Here i am including the model file part of this varactor and the hdl,( is that what you wanted to see?)
original hdl ******************** module rfCap(vp, vn); inout vp, vn; electrical vp, vn; real c,q; parameter real cgmin=1; parameter real dcg=1; parameter real dvgs=1; parameter real vgnorm=1; analog begin // c=cgmin+dcg*(1.0+tanh((V(vp ,vn)-dvgs)/vgnorm)); q=(cgmin+dcg)*V(vp, vn)+vgnorm*dcg*ln(cosh((V(vp, vn)-dvgs)/vgnorm)); // I(vp, vn) <+ ddt(c*V(vp, vn)); I(vp, vn) <+ ddt(q); end endmodule ****************************************** And this is how varactor is described in model file ************************************* HSPICE LEVEL 49: // // ## library files: // // The varactor are modeled with sub-circuit 'MOSCap_g3' and 'MOSCap_g6' // // Model name L(um) Wf(um) Side Branch Group // ---------------------------------------------------- // MOSCap_g3 0.5 2 2 50 3 // MOSCap_g6 0.5 2 2 50 6 // ---------------------------------------------------- // // Following is a poly gate of a varactor which has 3 Groups, 5 Branches. // There are 2 Sides of Branches in per Group. // // --+----+----+-- // -+- -+- -+- // -+- -+- -+- // -+- -+- -+- <<___Branch // -+- -+- -+- // -+- -+- -+- // ^ // ^---Group // // ************************************* // Varactor's Group number=3 * // ************************************* subckt moscap_g3 ( Gate Bulk ) parameters dt=temp - 25 + cgmin=0.95 * (1 + 3.503e-4 * dt + 1.071e-5 * (pow(dt,2))) * 1.0e-12 + dcg=1.029 * (1 - 6.564e-5 * dt + 1.836e-7 * (pow(dt,2))) * 1.0e-12 + dvgs= - 0.116 * (1 + 1.814e-3 * dt - 8.909e-6 * (pow(dt,2))) + vgnorm=0.456 * (1 + 9.656e-4 * dt - 1.841e-6 * (pow(dt,2))) lgate ( Gate 3 ) inductor l=36.6e-12 rgate ( 3 4 ) resistor r=0.7947 tc1=5.498e-3 tc2=8.1779e-6 cgate ( 4 5) rfCap cgmin=cgmin dcg=dcg dvgs=dvgs vgnorm=vgnorm rch ( 5 2 ) resistor r=1.4703 tc1=2.945e-3 tc2=2.9702e-5 cov ( 5 2 ) capacitor c=147.5e-12 csub ( 5 6 ) capacitor c=30.2e-15 rsub ( 6 0 ) resistor r=21.1820 tc1=9.396e-3 tc2=-4.9267e-6 rs ( 2 9 ) resistor r=0.7906 tc1=4.111e-3 tc2=3.9114e-6 ls ( 9 Bulk ) inductor l=19.3e-12 ends moscap_g3 ************************************** Thanks again --Vikas
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