Hisham
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Verilog-A: Instantiating Primitive Analog
Jul 26th, 2004, 3:35am
I am experimenting the verilog-A. Here is my simple code for implementing nmos by instantiating primitive nmos (modn) in my code:
`include "constants.h" `include "discipline.h" module nmos4(B, D, G, S); inout B,D,G,S; electrical B,D,G,S,Dr; real Idsn; mywire wr (D,Dr); modn nmos1 (Dr,G,S,B); analog begin Idsn=I(D,Dr); end endmodule
This is fine. But what I need to to be able to trace the tranconductace (gm) of the modn.
Please help
Hisham
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