Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Jul 21
st
, 2024, 9:26am
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Simulators
›
Circuit Simulators
› how to plot output resistance.
‹
Previous topic
|
Next topic
›
Pages: 1
how to plot output resistance. (Read 74 times)
forestmay
New Member
Offline
Posts: 3
how to plot output resistance.
Aug 06
th
, 2004, 10:27pm
In chapter 5 of EE240 ,Prof Boser plot the output resistance of cascode current and that with no cascode topology.i don't know how to plot such graph in Hspice. thanks for your advices in advance!
Back to top
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
»» Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.