Dear all,


    I am working on "Prediction of Glitches and Hazards at transistor level". I have to analyse glitches and develop metrics to predict them. The anaylsis will be done at transistor level and i have to implement a mechanism to record the incomplete transitions during simulation. To do this I am using various tools of Cadence.

I am generating the netlist (3 bit Adder for example) using synopsys design analyzer. I then create a schematic using Cadence Virtuoso and supply it with input streams. Later I analyse the outputs. This is what I am suppossed to do.

The problem :

1) How can I convert the inputs which are in binary digital format to analog voltages so that i can give them to my schematic as inputs. I have heard about this "BitGen" program which does this but never tried it. Any other Cadence alternatives you can suggest ?

2) How can I record the incomplete transitions during simulation at transistor level.

3) I have to estimate the Glitches and other parameters (like the No.of Glitches etc..). To do this i have to analyse the wave forms and i cannot do this manually. Can any one suggest any good alternative that i can use in this kind of a scenario. I have heard of "OCEAN" scripting language, SKILL, TCL etc.. can they be useful to analyse the wave forms.

4) Can i automate the whole above processes, instead of doing it manually. Like starting cadence tools (SpectreS simulator), giving inputs, and analysing outputs. If so how can i do that ?

A very lengthy post i believe. Please take some time for this newbie and help me out.

Thanks in advance,

kamesh.

P.S : pardon me if this is not the place to post this.

Thanks mightmouse.. but your answer is a bit vague for me considering the fact that I am new to this Cadence tools and scripting language. I have some knowledge of TCL and i have used synopsys design analyzer before.  

Adding more to my question above... to be precise i have to test some metrics to predict Glitches which were already developed on the basis of gate level simulation using Modelsim. Now i have to use the synthesis flow with the XFAB technology and test those metrics.

If possible could you please add some more in a detailed way. you forgot the incomplete transitions part.

Thanks in advance.
kamesh.

I'm afraid I don't know anything about synopsys design analyzer, modelsim, or XFAB technology. If you don't know anything about Verilog-AMS or Spectre netlist language this could be tough. Can you ask a more specific question that would help you get started?

- MM -

First off, the SpectreS iterface is really old and no longer preferred. It is better to use the Spectre interface.

I don't know artist well enough to know if it can sweep though 200 PWL files. You can try the parametric analysis capability, but I suspect it only sweeps numeric parameters. So instead I was suggesting that you could use a scripting language like Tcl to produce a netlist that caused Spectre to step through each file, and then run Spectre with that netlist standalone (outside Artist).

The file would look something like this ...
Code:

// run adder over a range of stimulus sets
simulator lang=spectre
include "adder.scs"
changeWave1 alter dev=Vin param="./waves/wave1.pwl"
tran1 tran stop=100ns
changeWave2 alter dev=Vin param="./waves/wave2.pwl"
tran2 tran stop=100ns
... 

This would run the circuit over all the input waveforms. The only thing left to do would be to detect the glitches. You can follow Ken's suggestions to write Verilog-A modules that you would include in your circuit. They would detect the glitches. From there you could either print out a message that ends up in the Spectre log file. Then you could use grep and wc to determine how many glitches occurred. Or you can have your Verilog-A module count the glitches and output the count directly to a dedicated file.

- MM -