Hi all I am trying to implement an automatic up/down counter. I have come up with the following code. It simulates fine but when I try to synthesis it the output just toggles between "0000" and "0001". Any suggestions on how to improve it.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity waves is
PORT(
reset,clk :in std_logic;
wave
![Shocked Shocked](https://designers-guide.org/forum/Templates/Forum/default/shocked.gif)
ut std_logic_vector (3 downto 0);
serialout : out std_logic
);
end waves;
architecture Behavioral of waves is
signal count_wire : std_logic_vector (3 downto 0);
signal e1 : std_logic;
signal shift : std_logic_vector (3 downto 0);
begin
count_proc: PROCESS(clk,e1,reset)
BEGIN
IF (reset = '1') THEN
count_wire <= "0000";
ELSIF (clk'EVENT AND clk = '1')THEN
IF e1 = '1' THEN
count_wire <= count_wire + 1;
else
count_wire <= count_wire - 1;
END IF;
END IF;
END PROCESS;
wave <= count_wire;
e1 <= '1' when count_wire = "0000" else
'0' when count_wire = "0111" else
e1;
END;