When you say "our circuit doesn't work" it's not clear what doesn't work...

As for the second example, my guess is that the CDL netlist you produced does not contain any AD, AS, PD, PS terms for the mosfets, whereas the spectre netlist probably does. So you probably have differences in the source/drain area and perimeter terms for the devices, which will alter the capacitances, and hence could alter the delay.

If you use a proper HSPICE interface (like hspiceD or the older hspiceS), rather than a netlist format that is intended for physical verification (where you would not be verifying source/drain areas), I suspect this problem would go away.

If this doesn't explain it, perhaps you could post the two netlists for the single inverter here? I guess they're not proprietary!

Regards,

Andrew.