Quite some experts in parallel computation and fast circuit simulation have worked on parallel simulation in the 80s and early 90s.

Xoomsys' claim is that some method from control system can solve the hard problem. I am just not sure whether it is applicable to all types of circuits or just a few types of circuits. For strongly coupled complex analog or mixed signal circuit, it is hard to imagine that one can partition it in such a way that not much communication is needed.

I don't know their product, but I guess you didn't get the way of operation of license servers with floating licenses...

Paul

All software vendors charge one license per computer. Oracle even insists on charging one license per core in the case of dual-core computers. Never heard of anyone who is willing to charge one license for users to run their software on 30 computers.

Indeed,

in the past 15 years there where approaches to speed up spices modified nodal circuit simulation. The parallel approaches are all depending on the algorithms. The device evaluation for instance could be run in parallel but for big size circuits the sparse matrix is dominating. Spectre does have application optimized code for doing that job. Parallel sparse matrix and multirate integration with latencies is the key. I think there is simply a manpower limitation to improve spice from the algorithm side. The parallel sparse matrix code today also show that the vector machines does not run them sucessfull. They are more powerful for FEM problems. Message passing architectures have latency issues. There is some drive from molecular dynamics where the problems have a similar sparse structure. I guess that this market would benefit more for the circuit simulation in future.

From the practical side use a single license on a liquid nitrogen cooled 3.2GHz FX-55.

For multicase verification use the licenses of the company and spread them over a number of boxes.

Organize your problem size and the verification hierachy scope that you get your result overnight.

I tried do catch up some informations about the technology but got nothing. I guess that they take a netlist and analyse how to separate the circuit. If the signal flow, analysed from the netlist, could be figured out as an directed tree then they could break up the netlist and simulate separate pieces. I am not shure that all supported simulators accept PWL sources for the interconnection signal flow with very high number of points.

This approach is similar to sparse matrix ordering methods but the difference is that from the netlist  information you only know what is I, O or IO. And this categorisation is seldom true for analog.

So wait 14 days. Then they should leak some information.

rf-design, thanks for the interesting reading.
I believe all the major simulator implement most of the tricks that Al mentioned and then some more. However, they all are stalled in terms of speed to where they've been some 10 years ago. It looks like Spice-like simulator developers gave up on speed problem with all the speed progress moved over to ultrasim and the likes.
Let's look if Xoomsys can change anything here.