Ken Kundert
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Dan, I took a look at the model and do not see an obvious explaination for the problems you are having. Though the model does have some obvious problems.
The most glaring is the use of the internal vdifdt node. Here, the derivative of the capacitor voltage is scaled by 1e-9 and converted to a voltage and applied to a node. This creates two problems. First, it is inefficient and slows the simulator. There is no need for this value to be a node voltage, and making it one causes the simulator to run slower. That voltage also affects the tolerance. If the slewrate on the capacitor ever goes higher than 1V/ns then the voltage on vdifdt will go above 1V, which with default settings, will loosen the tolerances on all voltages in the circuit. To avoid this problem, you should use relref=siglocal.
The second problem with the model is that it is inefficiently implemented. Code optimization is not very advanced in Verilog-A compilers, and so people writing models should optimize their models by hand.
The third, and most significant problem in the model, is that the model does not conserve charge. This is especially damaging in charge storage circuits, such as your auto-zero circuit. To see a good example of the problems caused by non-charge-conserving models, take a look at page 167 in my Spice & Spectre book.
However, none of these problems should be made substantially worse when using Monte Carlo.
-Ken
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