I am simulating a circuit that contains a MOS varactor with a verilogA model.  When I run a normal transient simulation I get no errors or warnings and spectre finishes in less than 1 minute.  When I run a Monte Carlo (mismatch only) simulation, each tran run takes 17 minutes and is full of minimum time step warnings.  The varactor is part of an ST design kit (I didn't write the model) and uses several files, but from what I can gather the core of the model is:
V(vdifdt) <+ ddt(V(plus,minus))*1e-9 ;
I(plus,minus)  <+  cvalue*V(vdifdt)*1e9;
where cvalue is some function of the tuning voltage.  Is there some way to figure out what is causing the minimum time step warnings?  I am runing with the default (moderate) error tolerances.  Changing to liberal gets rid of the time step warnings but results are quite different.  Thanks in advance to anyone who can offer help.

cvalue is too complex a function of the control voltage for me to integrate analytically (if-then statements) so I'm not sure how to rewrite the model as sugested in the varactor paper.  Can I do a numerical integration?  Any thoughts on why I only see warnings durring Monte Carlo?  If I end up staying with the existing (non-charge conserving, but supported) model, what can I do to verify that it is accurate enough?  I am using the varactor as a coupling capacitor in an autozeroing network, so I'm a little worried about the effect of switching transients on that vdift expression.  Thanks again for the help.

The varactor is definately causing it.  I've run the sim many times with linear metal capacitors and never seen this problem.  I want to use the varactor because of it's high capacatince density, but in order to do that I've got to have confidence in the models.  Guess I might have to eat the area and use metal.

There is no way to compute the integral symbolically in Verilog-A. You can do it in Matlab and code it into Verilog-A.

If the slowness is not caused by ringing or parasitic oscillations, and it goes away when you use a linear capacitor, it may be a result of errors or discontinuities in the model.

Can you post the model?

-Ken

Dan,
   I took a look at the model and do not see an obvious explaination for the problems you are having. Though the model does have some obvious problems.

The most glaring is the use of the internal vdifdt node. Here, the derivative of the capacitor voltage is scaled by 1e-9 and converted to a voltage and applied to a node. This creates two problems. First, it is inefficient and slows the simulator. There is no need for this value to be a node voltage, and making it one causes the simulator to run slower. That voltage also affects the tolerance. If the slewrate on the capacitor ever goes higher than 1V/ns then the voltage on vdifdt will go above 1V, which with default settings, will loosen the tolerances on all voltages in the circuit. To avoid this problem, you should use relref=siglocal.

The second problem with the model is that it is inefficiently implemented. Code optimization is not very advanced in Verilog-A compilers, and so people writing models should optimize their models by hand.

The third, and most significant problem in the model, is that the model does not conserve charge. This is especially damaging in charge storage circuits, such as your auto-zero circuit. To see a good example of the problems caused by non-charge-conserving models, take a look at page 167 in my Spice & Spectre book.

However, none of these problems should be made substantially worse when using Monte Carlo.

-Ken

Whoops. Use 'alllocal'.

-Ken

Ken -
You wrote:
Quote:


but this leaves off the ddt in the original model.  I assume you meant

   I(plus,minus) <+ cvalue*ddt(V(plus,minus));

And, to address the non-charge-conserving question, one might try:

  I(plus,minus) <+ ddt(cvalue*V(plus,minus));

It's possible that the original equations for "cvalue" were derived with this in mind.

-Geoffrey