sheldon
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Andrew,
Guess it is a matter of perspective. Since the tool provides IR drops plotted on the "extracted" layout, effectively, it provides you the sensitive regions in the layout. If you always follow good design practices, differential signal paths, star grounds, routing bias currents, etc, then the regions with noisy power supplies are most likely regions where there are supply noise issues.
Back to the original question, there was a technology from OpMaxx --> Fluence --> IMS --> Credence called DesignMaxx that calculated the sensitivities of the circuit matrix using the adjoint matrix. This technology would allow you to quickly calculate the sensitivities of the output to the nodes in the circuit. However, aren't there some issues with this approach? For example, do all parameters have the same sensitivity to layout parasitics? Or do you need to do a sensitivity analysis for each design parameter? How are you going to capture and use the layout constraints, particularly, if the each parameter is sensitive to the parasitics at different nodes?
To look at the problem the other way around, why aren't there tools for analog virtual prototyping? Doesn't it make more sense to concurrently design the circuit and the layout? Maybe it is just me but it seems like the best solution to this problem is to be proactive, i.e., use analog virtual prototyping.
Best Regards,
Sheldon
P.S. For more information on the DesignMaxx approach, see IEEExplore and search for limsoft, that was the name of the Analog BIST tool DesignMaxx was integrated into.
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