The main premise of paper RF Simulation Challenges
(can be found in www.designers-guide.org/Perspective/
) is that the simulation challenge is getting harder in many different dimensions at once:
- circuits are becoming larger
- circuits are becoming more "algorithmic", meaning that they are tending to implement algorithms with complex behavior (such as delta-sigma converters, fractional-N synthesis, etc.), with the result being that many more cycle need be simulated
- circuits exhibit many more modes, all of which must be exercised by simulation
- circuits must be verified over increasing numbers of corner cases, or perhaps using Monte Carlo.
- circuits are becoming increasingly diverse, meaning that special purpose algorithms that exploit particular characteristics of circuits to provide faster simulation, such as is the case with RF simulators, become increasingly ineffective
- with designs becoming more complex and design teams becoming larger, it is increasingly important to move the verification task earlier in the design process to catch and correct errors sooner, thus verification must occur before all circuits are designed and working at transistor level
In parallel to these trends are the ones you mention, that the performance gains of individual processors is leveling off, that computer makers will increasingly move to multiprocessor systems, and that circuit simulators in the past have been relatively unsucessful at taking full advantage of multiprocessors.
My belief is that simulation companies will begin to recognize the trend towards multiprocessors and slowly start to offer products that take advantage of them. The low hanging fruit will be to run multiple independent simulations simultaneously. You can do that today when doing corners and monte carlo, though current products are rather clunky. I hope that they also recognize the issue with multiple modes and multiple measurements and start allowing those to be easily run in parallel.
Simulators that actually distribute a single simulation to multiple processors will eventually emerge. Expect them to emerge in the specialty simulator areas first, where parallelism is easier to exploit. So I would expect parallel RF and timing simulators to become available before parallel SPICE simulators.
I also expect RF simulators to try to adapt to the increasing diversity in the circuits, with limited success. Timing simulators will also try to take on more analog, mixed-signal and RF circuits. They will have more success, but will never replace the SPICE and RF simulators if for no other reasons than the AC and noise analyses remain important.
None of this will allow the effective speed of simulators to keep up with increasing need for verification. So I expect design groups will turn more and more to top-down verification, which is a methodology that allows simulation speed to increase dramatically through the use of high-level modeling (see Principles of Top-Down Mixed-Signal Design
). This does require that designers be more deliberative in planning their verification, but has the important side benefit in that it produces an accurate high-level model of the mixed-signal portion of the design, which can be shared with the digital designers that must use the mixed-signal design.