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Using variables in structural elements. (Read 2965 times)
Eugene
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Using variables in structural elements.
Jul 27th, 2005, 7:48pm
 
Experimentation shows that with Cadence's Spectre/VerilogA, it is not possible to use a variable in a structural element. I tried using a variable for the resistance of a structural resistor. A behavioral block set the variable. It seems Spectre always set the structural resistor to zero ohms. However, I received no errors or warnings, just wrong answers. I would expect the syntax checker to catch such an error. Does anyone know for sure that VerilogA does not support variables in the parameter fields of structural elements?
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Geoffrey_Coram
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Re: Using variables in structural elements.
Reply #1 - Jul 28th, 2005, 12:55pm
 
Eugene -
You are correct: you can't use a variable.  Variables do not get initialized until the simulation begins, but structural elements are placed (and their parameters determined) at "elaboration" time.

It's a little odd in an analog simulator, since we like to sweep model parameters, so we don't think of them as "constants" as does the rest of the Verilog world.

You should be able to use an expression involving only parameters of the main module and get a non-zero value.

-Geoffrey
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Eugene
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Re: Using variables in structural elements.
Reply #2 - Jul 28th, 2005, 1:28pm
 
In that case, I think the syntax parser should have flagged the problem before the simulation.  I guess this also means I can not make the structural parameter depend on a node voltage either.  Anyway, thanks for the confirmation Geoffrey.
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jbdavid
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Re: Using variables in structural elements.
Reply #3 - Aug 3rd, 2006, 6:38am
 
not in verilog a, but in spectre you could use a bsource device..

resistor #(.r(Rfixed) R1 (A, B);

cant vary- its just a spectre resistor..
real Rvary
Rvary = V(in)*2;
V(A,B) <+ I(A,B)*Rvary; // same thing, but Resistance varies with V(in);

Youi can't make the structure vary with conditions any more than you can make the silicon change with voltages..
you can turn switches on and off with voltages but you cant rewire a circuit for voltage changes..
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jbdavid
Mixed Signal Design Verification
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