Im simulating a large analog chip at present and getting a little weary of trying to get this running using a combination of models/HDL's. Even when it does start running, Im not comfortable that the results are meaningful due to the number of approximations and compromises I have to make. Simulating the pieces is fine, but combining these into an accurate system level simulation is driving me nuts.

I really need spice level simulation throughout. Anyone done an evaluation of true fast spice simulators?

By 'true' I mean that the simulation is accurate in both time and voltage/current axes. I see a lot of claims about tools such as HSIM, but these are a bit misleading since hierarchical tools such as this only appear to work well where there is significant repetition in the design. In large chips which are predominantly analogue, such tools really dont deliver.

I guess the holy grail of simulation would be full chip simulation at spice accuracy with short simulation times. Obviously CAD vendors have been chasing this goal for many years and maybe it will never happen, but which simulators are the closest to this ideal?

From press reports it sounds like Avanti's Star-SimXT is the first in line. Experiences on this subject anyone?

Godfrey,

the feature of HSIM to simulate a number of parallel connected identical subcircuits only once and then divide the current by the number of instances is a small feature. This HSIM implementation is simply the replication of the simulation technique long time ago in practice to simulate memory circuits. The advantage is now that the netlist reader and matrix stamp engine doing the work now. Also if there are different initial states the reader handels that properly.

The other advantage of HSIM is that it support true hiearchical tolerance setting. So you can have circuit type depending settings. That improve the speed a little bit. If you use the same accuracy as spice for all node voltages and currents HSIM is slower than the industry standard. So comparing only the speed of the full chip simulation and cover all possible mailfunction (parametric, functional, missconnection, misinterpretation,...) you have to use many levels of simulation descriptions. At each level you can improve level of confidence. So describing that with tools or languages:

Matlab+Simulink+VerilogA+HSIM+Spectre

I share the view that also full chip spice is needed to verify special interaction effects. But the key is to minimize the number of these simulations and indication to run redesign loops through higher levels.

For future design with sticked CPU powers there is the need for parallel processing spice with multirate/multiresolution simulation. That does not exist in research either.