My off the cuff answer is to write a verilog-A model that dumps the sample to a text file during the simulation.. This was how I did it when using SPW to do the calculations for a tutorial on ADC simulation with Verilog-AMS I presented at BMAS (
http://www.bmas-conf.org) back in 2002. In fact the model may have made it into the "bmslib" added to the cadence tool set in 2004 (5.0.32+) look for SignalSink..
If I had access to that database, I could post the model here..
but the basic idea is simple.. same as any DAC model, except instead of setting an analog output you use $fstrobe to write the output code to a file for post-processing..
Jonathan