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Eugene

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mixing behavioral and device level models
Oct 20^th, 2005, 2:32pm

One of the primary motivations for building behavioral models is to reduce simulation time by simplifying blocks that are not of immediate interest. �Unfortunately, I am running into some pretty elusive convergence problems when I mix behavioral and device level models. The simulation runs fast when everything is modeled behaviorally. The simulation runs slow when everything is modeled at the device level, but at least it runs. When I mix the two models, the simulation hangs at the power up command. I can not post any more details without exposing IP, other than to say the devices are cmos devices and that the circuit is a receiver chain. The strange thing is that in some cases the device level and behavioral models do not even have to be connected to cause DC convergence problems. I was wondering if anyone else has encountered these kinds of convergence problem when mixing device level and behavioral models and if so, are there any general guidelines that would help?

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rf-design Senior Member Offline Reiner Franke Posts: 165 Germany	Re: mixing behavioral and device level models Reply #1 - Oct 20^th, 2005, 11:00pm My practical experience is that if the models are too optimistic (gain, linearity, no limitations) that these lead to convergence issues at .OP. After finding the right OPs transient is much more easier.
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Ken Kundert

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Re: mixing behavioral and device level models
Reply #2 - Oct 21^st, 2005, 9:22am

Of course the possiblilities are endless, and without knowing more about your circuit we are just guessing. Having said that, let me throw out a possible issue.

If the behavioral model generated a signals with an infinitely fast rise time (if no transition function were used), then the simulator would tend to ignore the issue if the model were connected to another behavioral model, but it were connected to a device model that exhibits input capacitance, then the simulator will try to shrink the time step to accurately compute the voltage waveform on the capacitor. With an infinitely fast rise time, the simulator will appear to hang or produce a "time step too small error".

Of course that requires the behavioral model and the device-level models be connected to each other.

However, if the circuit had a very fast unstable pole, the simulator might not notice it unless the timestep was made very small. And it could be the behavioral model that is forcing the small time step. This is described starting on page 219 of my Spice and Spectre book. You can determine if this is occuring by using diagnose=yes option and look for exploding signals.

-Ken

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Eugene

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Re: mixing behavioral and device level models
Reply #3 - Oct 21^st, 2005, 10:43am

Thanks for the responses.

rf-design,
Interestingly, the problem often disappears when I remove the nonlinearity from the behavioral model.

Ken,
Thanks for the "diagnose=yes" tip but I'm pretty sure the behavioral model is stable because if I remove the device level model, the simulation has no problem. In fact, both the behavioral and device level models run just fine by themselves. It's only when they are in the same schematic that I see the problem and as I said before, the really baffling part is that they are not connected in any way. I'll take a look at page 219.

I should add that I could not use the transition statement because the model had to be compatible with SpectreRF and I believe the transition filter has hidden state.

For now, I've sovled the problem by simplifying the behavioral model and giving the behavioral op amp a more realistic output resistance.

All,
On a related thought, I'd be interested in whether either of you think I'm right in saying that in general, circuit simulators were optimzed for device level models and consequently, as a VerilogA model of the same circuit captures more and more detail, it actually runs slower than the original device level �model. It is even possible that the VerilogA model could eventually fail to converge. Does that sound about right?

-Eugene

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Paul

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Re: mixing behavioral and device level models
Reply #4 - Oct 21^st, 2005, 3:00pm

Hi Eugene,

[quote author=Eugene link=1129843934/0#3 date=1129916621]
..., circuit simulators were optimzed for device level models and consequently, as a VerilogA model of the same circuit captures more and more detail, it actually runs slower than the original device level model. [/quote]

I somewhat agree with your considerations. We must not forget that the simulator-device model combination has been optimized for several decades to reach its current performance. I just wonder in how far your criticism of simulators is justified, as I believe that a lot of effort has been spent on improving the convergence of the device models. Can we purely blame the EDA tool providers or must we, model designers, learn how to write "convergeable" (sorry, I could not find the appropriate word for this) models?

Looking forward to read your point of view...

Paul

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Eugene

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Re: mixing behavioral and device level models
Reply #5 - Oct 21^st, 2005, 4:30pm

Paul,

Thanks for your comments. I agree. We as model developers must learn to make models that converge. Furthermore, I think the tool providers did the right thing in optimizing simulators for devices instead of VerilogA. After all, in the end we want to verify the actual circuit, not the VerilogA version of it.

I did not mean to criticize simulators or blame anyone by posing my question. I only meant to explore the limits of the trade off between speed and accuracy. In the accuracy limit, the VerilogA model would exactly duplicate device level behavior. But in that limit, I wonder if the VerilogA model would actually run slower. If so, the VerilogA model must sacrifice some accuracy just to match the speed of the device level model. With a better understanding the simulator's limitations regarding VerilogA, I hope to waste less time struggling to model details that are best left to the device level models.

-Eugene

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Eugene

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Re: mixing behavioral and device level models
Reply #6 - Oct 21^st, 2005, 7:48pm

Ken,

I read section 4.4.6 of your book. Section 4.4.6 covers macro models. I am indeed using a macro model. Your comments were exactly the type of guidelines I wanted. Unfortunately, none of them covered the DC convergence problem I encountered. But to be fair, I did find a problem with the thresholds I was using for a couple of ideal switch models. It was still strange that the two unconnected faulty behavioral models together converged while the combination of one faulty behavioral and one device level model did not converge...DC wise. I mention this only incidentally. I've since managed to make the models much more robust.

-Eugene

P.S. After reading section 4.4.6 I performed an AC stability analysis on the op amp and it was stable. You may have been right about the sharp edges. For the power up problem, I suspect the increased output resistance slowed the charging of some parsitic capacitance in the device model. In the power up example, the models were connected. Thanks for the help.

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« Last Edit: Oct 22^nd, 2005, 1:14am by Eugene »

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