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VCO jitter (Read 6568 times)
shiva
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VCO jitter
Nov 07th, 2005, 7:00am
 

Hello,

I know it's a pretty open question, but I'm a bit stuck, so here it goes: anyone has a good idea/reference on how to model the phase noise/jitter of a VCO using VHDL-AMS?

Kind Regards

Peter
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Ken Kundert
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Re: VCO jitter
Reply #1 - Nov 7th, 2005, 11:40am
 
Check out http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf.

It describes how to build such a model for Verilog-AMS. It should be a simple matter to translate the model to VHDL-AMS.

-Ken
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Amrsfmt
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Re: VCO jitter
Reply #2 - Mar 20th, 2006, 12:21pm
 
Hi,
Actually, I tried this in VHDL-AMS, but failed because simply there is no function named phase_noise or noise in VHDL-AMS. I know there is noise sources but not implemented in All tools. For example, the ADMS don't implement the noise sources in VHDL-AMS.

There is 2 solutions for noise:
1- create a noise source in sub-circuit in ELDO spice, and instantiate it in your code and used it in a structural discribtion with your ideal model.

2- create the noise by yourself.

Actually, I made both solutions.

Here is a sin source with noise on it in transient , no noise in AC. Read the code if there is something please post.
Amro
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Paul
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Re: VCO jitter
Reply #3 - Mar 21st, 2006, 2:16pm
 
Hi,

I am using a ring oscillator model in an event-driven fashion (i.e. the output is a square-wave). In that case, you can simply calculate the delay to the next edge and include a random component. The interesting thing is that this uses pure VHDL (or Verilog of course) and doesn't need the AMS extensions.
If you want a sine-wave output, you may use a random signal based on the random number generator and use it to phase modulate your sine wave.

Paul
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Re: VCO jitter
Reply #4 - Mar 21st, 2006, 2:53pm
 
HI,
That's exactly what I have made in the code above.

Thank you,
Amro
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