sheldon
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Steven, The yield that was referred to is parametric yield and does not include failures due to random manufacturing defects. Design margin is the how much "better" than the specification the design is. For example, if the offset specification is < 10mV and mismatch analysis says that the standard deviation of the offset voltage, sigma, is 1mV[with 0V mean], then the design has a lot of margin, 10 sigma. If mismatch analysis says that the offset voltage sigma is 4mV, then the design margin is 2.5 sigma. There is potentially a yield loss problem due to offset voltage. Whether or not this yield loss is really problem, is a very subjective decision. For example, some die will fail by design, however, the yield loss may be canceled out by the other benefits, for example, smaller die size --> more die/wafer --> more good die.
In practice, analog and mixed-signal[A/MS] circuit designers don't simulate the effect of random manufacturing defects on their designs.
Monte Carlo analysis estimates a parameters distribution with process variations and mismatch [given statistical models] so the yield and design margin can be calculated. In addition, Monte Carlo analysis allows you to analyze the correlation between circuit performance and process variations.
Statistical modeling is hard to describe simply, please see the following references for some discussion of the issues related to accurately modeling statistical process variation. "Generation of Correlated Parameters for Statistical Circuit Simulation", K. Eshbaugh, TCAD, October 1992 "An Asymptotically Constant, Linearly Bounded Methodology for the Statistical Simulation of Analog Circuits including Component Mismatch Effects", C. Guardini, et al, DAC 2000 "Analysis of Mixed-Signal Manufacturability with Statistical Technology CAD(TCAD)", D. Hanson, et al, Transactions of Semiconductor Manufacturing, Nov. 1996 These papers discuss the statistical tools used to determine which parameters are important.
Paul is correct that passing corner analysis does provide confidence that the design will have good yield in production. However, my previous comments about corner analysis reflect the following concerns:
1) My part fails the slow corner. If the power needs to increase by 25% to pass the slow corner is my design bettter? The issue is that failing the corner does not tell me what impact the failure has, is yield 99% is yield 0%? Losing 1% of the die to decrease power dissipation by 25% may be a good thing.
2) My process has fast/slow corners[minimum/maximum gate length] and my next design will operate at 1V, that is, Vt variation defines the worst/base corner conditions. Will the current corner models accurately predict yield?
Corner analysis[as currently practiced] is a useful tool for design verification, however, it may not provide designers enough information.
Finally, back to the question in your original post. It is very difficult for designers to generate mismatch models that are accurate. The models should come from the foundry and the model development team. As an example, for a bipolar transistor Beta, Va, ft, and rb are all correlated so you can not just mismatch Beta by +/-10% and expect good results. You would need to vary all the parameters together. The issue is that by varying just one model parameter without considering the relationship between the model parameters, the resulting models may be non-physical. Non-physical means that the model may contain combinations of model parameters that do not occur during normal manufacturing. Non-physical models produce simulaton results that are not silicon-accurate, that will not occur in production, and these results can skew the distributions.
You can implement the Spectre statistical simulation methodology in SPICE. However, it will require a lot of manual manupulation of the model files. For a simpler approach to mismatch modeling, please look at Spectre's DC Mismatch analysis.
Best Regards,
Sheldon
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