Hello,

I browsed through the posts on Monte Carlo (MC) simulation. If I understand the process correctly, the mismatches are simulated through MC and certain statistic distribution functions, e.g., from Shelton's post. Now if I don't have Spectre but only Spice simulator, I am wondering what parameter mismatches are usually simulated. For instance, beta in transistors. I read some papers on statistical simulation but don't get the key what are the pivotal parameters to focus on.

Thanks in advance.

Hello Paul,

Thanks for your enlightening post. No wonder why the worst case simulations (maybe also called corner simulations) are so time consuming due to individual component modeling. My previous comprehension on statistical simulation was that the componet model would concertrate certain parameters with certain distribution function, e.g., Gaussian with x-sigma derivation. However, there are too many parameters need to be modeled. There comes statistical simulation to narrow down the key ones. So I was very curious how real simulations are performed. Your post gave some flavor on this.

By the way, I think you had a typo in your post: the Eldo RF manaul has only 13 chapters. But it is easy to locate the syntax related to the topic here. Appreciate your sharing.

Steven,

  Usually corner analysis does not include device mismatch. Monte
Carlo simulation does include device mismatch.  

  It might help to think of corner analysis as Extreme Value Analysis,
what is the effect of the largest variation in transistor characteristics
that occurs in the process on circuit performance. For digital circuits,
the largest variation is relatively easy to define, that is, fast and slow.  
In the case of corner analysis, the models for all transistors are set
to corner conditions at the same time, that is, no mismatch. BTW,
Spectre does support mismatch extreme value analysis, the analysis
is called dc mismatch. DC mismatch mismatches the devices in
diff pairs and current mirrors by 3 sigma and calculates the sensitivity
of the ouput to mismatch. The main limitation of dc mismatch analysis
is that only dc and small signal analysis are supported.

 Also the results from corner analysis and Monte Carlo analysis, provide
us different information about the circuit. Corner analysis tells us whether
or not the circuit meets a specification but provides no information about
yield or design margin. Monte Carlo analysis provides all detailed
nformation about design margin and yield.

                                                                  Best Regards,

                                                                      Sheldon

Hi Sheldon,
I find it misleading for the non-expert reader to say that MC provides yield information while corner analysis doesn't. As you say, both types of analysis provide different information, and both are important to perform. However, both may provide yield information if run in a statistical fashion, which unfortunately isn't frequently done for corner analysis.

As a complement to your post: Monte-Carlo analysis performs statistical variation of device parameters, according to standard deviation and mean values usually determined for matched devices in close vicinity. As such, it analyses matching issues due to intra-die variations. Corner analysis on the other hand varies device parameters of all identical devices in the circuit in the same fashion. It analyses the robustness of the design to process variations. The parameter variations in the second case are of course much larger compared to  MC. These process variations may appear when you perform one integration today and the second in six month (or two years), possibly using different equipement in the same fab and so...

It should also be mentioned that Monte Carlo is the name of the statistical analysis method (and not the mismatch analysis itself), i.e. the tool can also be used to perform statistical process variation analysis. As the statistical parameters are usually not included in the design kit, it is up to the designer (or CAD engineer) to extract them from the corner information. With these parameters, you can run yield analysis over process variations.

To Steven's question: Yield defines how many circuits will work in specs out of the number of manufactured devices. Frequently yield of a mature design is supposed to exceed 90%, but a reasonable yield value depends on the die size and the application (e.g. yield is lower on high-end microprocessors than for 8-bit microcontrollers).

Best,

Paul

Steven,

The yield that was referred to is parametric yield and does not include failures due to random manufacturing
defects.  Design margin is the how much "better" than the specification the design is. For example, if the
offset specification is  < 10mV and mismatch analysis says that the standard deviation of the offset voltage,
sigma, is 1mV[with 0V mean], then the design has a lot of margin, 10 sigma. If mismatch analysis says that
the offset voltage sigma is 4mV, then the design margin is 2.5 sigma. There is potentially a yield loss problem
due to offset voltage. Whether or not this yield loss is really problem, is a very subjective decision. For example,
some die will fail by design, however, the yield loss may be canceled out by the other benefits, for example,
smaller die size --> more die/wafer --> more good die.  

In practice, analog and mixed-signal[A/MS] circuit designers don't simulate the effect of random manufacturing
defects on their designs.  

Monte Carlo analysis estimates a parameters distribution with process variations and mismatch
[given statistical models] so the yield and design margin can be calculated. In addition, Monte Carlo
analysis allows you to analyze the correlation between circuit performance  and process variations.

Statistical modeling is hard to describe simply, please see the following references for some discussion of the
issues related to accurately modeling statistical process variation.
"Generation of Correlated Parameters for Statistical Circuit Simulation", K. Eshbaugh, TCAD, October 1992
"An Asymptotically Constant, Linearly Bounded Methodology for the Statistical Simulation of Analog Circuits
including Component Mismatch Effects",  C. Guardini, et al, DAC 2000
"Analysis of Mixed-Signal Manufacturability with Statistical Technology CAD(TCAD)", D. Hanson, et al,
Transactions of Semiconductor Manufacturing, Nov. 1996
These papers discuss the statistical tools used to determine which parameters are important.

  Paul is correct that passing corner analysis does provide confidence that the design will have
good yield in production. However, my previous comments about corner analysis reflect the
following concerns:

1) My part fails the slow corner. If the power needs to increase by 25% to pass the slow corner
   is my design bettter?
   The issue is that failing the corner does not tell me what impact the failure has, is yield 99%
   is yield 0%?  Losing 1% of the die to decrease power dissipation by 25% may be a good thing.

2) My process has fast/slow corners[minimum/maximum gate length] and my next design will
   operate at 1V, that is, Vt variation defines the worst/base corner conditions. Will the current
   corner models accurately predict yield?

   Corner analysis[as currently practiced] is a useful tool for design verification, however, it may not
provide designers enough information.

Finally, back to the question in your original post. It is very difficult for designers to generate mismatch models that
are accurate. The models should come from the foundry and the model development team. As an example, for a
bipolar transistor Beta, Va, ft, and rb are all correlated so you can not just mismatch Beta by +/-10% and expect good
results. You would need to vary all the parameters together. The issue is that by varying just one model parameter
without considering the relationship between the model parameters, the resulting models may be non-physical.
Non-physical means that the model may contain combinations of model parameters that do not occur during normal
manufacturing. Non-physical models produce simulaton results that are not silicon-accurate, that will not occur
in production, and these results can skew the distributions.

You can implement the Spectre statistical simulation methodology in SPICE. However, it will require a lot of manual
manupulation of the model files. For a simpler approach to mismatch modeling, please look at Spectre's DC Mismatch
analysis.

                                                                                                                  Best Regards,

                                                                                                                    Sheldon

Hello Sheldon,

Thanks a lot for your detail explanation. I also took a look at the paper by Eshbaugh and further curious on the statistical simulator design. As explained in the paper, all the key roots in availability of correlation matrix R and raw data set x. Then transformation from x to Gaussian doman data y would further explore the mulivariarate of Chi-square distribution of other parameters. This is the standing point of MC simulation. In the example, it has been demonstrated that with three key parameters, the method would generate the distribution of the device. So the process would be better considered as a post-measure processing.

However, if the above understanding is correct, I am not clear on two processes here:

First, the raw data set must be measured even though the later part of the paper stated that extraction of MC may help. How can the extraction obtain the raw data? It seems to me a loop: simulation produces "raw" data and then use "raw" data to predict the distribution. There must be something I missed.

Second, this one is a little too far from the topic but anyhow I just list it out. In the proposed method, numerical methods have been adopted to obtain mulitvariate Gaussian distribution. It is well-known that these methods would produce errors. The would be even worst if some correlation coefficients are so small that they might be dropped out during numerical processing such as diagonization. So I would ask, in real simulation tools, e.g., Spectre (I have never used it), how close is the simulation results to those of measurements (of course, roughly speaking). In other words, how much you would trust the simulation results, say from the MC simulation? I would guess the answer may lie on the yield and design margin you mention but need you confirm.

Luckily enough can learn so much from all of you here.

Regards,
Steven