achim.graupner
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Hi there,
I am designing an SC-ADC with some kind of sophisticated clocking. Thus I have about 10-20 clock signals. Now I want to do an PSS/Pac/Pnoise analysis. Usually I use an automatically generated VerilogA-Model which provides all the required clock signals like in the following code:
@(timer(4*t_delay, t_period)) begin t_getph = vdd; end; @(timer(4*t_delay+t_period/2, t_period)) begin t_getph = 0; end; ... V(getph) <+ transition(t_getph , 0, 1n, 1n);
With this code PSS termiated with an error because of the hidden state in the model. If I however change the code to (see the ?: assignment in $transition)
@(timer(4*t_delay, t_period)) begin t_getph = 1; end; @(timer(4*t_delay+t_period/2, t_period)) begin t_getph = 0; end; ... V(getph) <+ transition(t_getph ?vdd:0, 0, 1n, 1n);
PSS runs without comment. The result however is not satisfactory. It seem as clock signal generated as above is not considered during the simulation.
Does someone has an idea how to automatically (at least to a large extent) generate a complex clock regime. The only idea I have so far is to use PWL-sources reading in some generated waveform. This however requires quite some effort (generating individual waveform-data, generate an VerilogA-view instanciating the PWL source etc.) and I am not quite sure whether this approach will work.
Any help is greatly appreciated.
Achim
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