paguirre
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Hi, Im using ASSURA 3.1.4 (first time using Assura) and i can't get it to see my pins in the layout.
Super simple example: 1 nmos with 3 pins: gate, drain and bulk/source. When i do the DRC i get a Floating gate error (ERC) which with Diva was gone when i added the gate pin. When i do the LVS i get that the only difference are the pins since the layout view is extracted with 3 automatically generated names instead of my pin's names.
I have tried both kinds of pins: sym pin and shape pin and even plain labels, all in met1 layer both drawing and pin type, but nothing seems to work.
I have been through the drc.rul file from my foundry, and everything seems ok as far as i can tell (reading the assuracomandref.pdf). The extraction of the sym pins for example is made with the following line: MET1_sympin = pinLayer( "MET1" type( "pin")) which is then merged with other derived layers into net_met1 which is the layer used in the connection statements.
Probably i'm not giving enough information (there's so much), please tell me what else should i post to help you guys help me ;)
Thank you very much, PA
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