Quote: 1. It is true that I must have a phase domain model to analysis PLL AC response(loop gain and phase margin), and then I have to build another voltage domain model to analysis PLL's transient response?
I believe the alternative is to apply a pss/pac analysis to the closed loop voltage domain model. There is a similar discussion regarding power supplies. Look under "High-Power Design/DC/DC Buck's Phase Margin analysis using spectre ?". However, I think your biggest problem here would be in getting the pss analysis to converge for a closed phaselock loop. I've heard it can be done but I'd bet it takes some effort, perhaps more than the effort required to build a phase domain model. I have also not heard whether the loop gain from the subsequent pac analysis is correct. It's something I always wanted to try. By the way, depending on the problems you want to study, the phase domain models may meet your transient needs too. The phase domain models are nonlinear and can do a fair job of simulating transient responses in a very small fraction of the time a voltage domain model takes.
Quote:2. How did you guys proceed the AC analysis on a PLL in general case. Will you build up a verilog-A model, or you just do it directly with actual schematic? If I do it directly, will it take very long machine time.
Is this the same question as #1? If you are building the model from the schematic, I assume you are using device level model, which must be a voltage domain model. AC analysis will not give you any meaningful results from a voltage domain model.
Quote:Ken can correct me if my answer is outdated but I believe Ken's paper describes a voltage domain model. However, I believe Ken used a phase domain model to generate any transfer functions that appear in the paper. I would have to re-read the paper to be 100% sure though.
-Jess