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Multiple modules in verilog (Read 2675 times)
ness9660
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Multiple modules in verilog
Mar 21st, 2006, 3:12pm
 
Ive always just been a c/c++ and java programmer.  So the idea of using functions is only natural to me, but the following code does not want to work in xilinx.  

Lets say Im going to make a 8x1 mux using two 4x1 muxes and a 2x1.  Can I just use modules in the same manner as c/c++?  For example

Code:
module mux_8x1(i0, i1, i2, i3, i4, i5, i6, i7, c0, c1, c2, result);
	input i0, i1, i2, i3, i4, i5, i6, i7, c0, c1, c2;
	output result;
	wire temp1, temp2;

		mux_4x1(i0, i1, i2, i3, c1, c0, temp1);
		mux_4x1(i4, i5, i6, i7, c1, c0, temp2);
		mux_2x1(temp1, temp2, c2, result);

endmodule

module mux_2x1(in1, in2, sel, out);
    input in1;
    input in2;
    input sel;
    output out;

	 wire a, b;

	 and(a, sel, in1);
	 and(b, ~sel, in2);
	 or(out, a, b);

endmodule


module mux_4x1(in0, in1, in2, in3, sel1, sel2, out);
    input in0;
    input in1;
    input in2;
    input in3;
    input sel1;
    input sel2;
    output out;

	 assign out= (in3 && sel2 && sel1) || (in2 && sel2 && ~sel1) || (in1 && ~sel2 && sel1) || (in0 && ~sel2 && ~sel1);


endmodule

 



In that example all three modules are contained within mux8x1.v, but this will does not seem to work.


I cant find any resources online.  Whats the proper way to use multiple modules?
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Geoffrey_Coram
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Re: Multiple modules in verilog
Reply #1 - Mar 22nd, 2006, 9:06am
 
You want to instantiate the sub-elements in the main module, not call them like functions.
Something like

 mux_4x1 mymuxa(i0, i1, i2, i3, c1, c0, temp1);
 mux_4x1 mymuxb(i4, i5, i6, i7, c1, c0, temp2);
 mux_2x1 mymuxc (temp1, temp2, c2, result);

Same sort of thing has to be done in mux_2x1 for the "and" and "or", I think.  (Where are they defined?)


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