Generally most designers, given some experience, think carefully of the physical design (layout)when designing at the schematic stage. This is especially true in RFIC design.
For example, designing an LNA in the schematic stage should have more gain and better NF than specification, knowing that the layout will tend to degrade both these figures of merit. The estimation of the parasitics (metal R & C, corsstalk etc.) in advance of the full alyout can be estimated from the process data or with a trial layout, and salient/sensitive net parasictics can inserted into the schematic as parasitic devices to help the schematic design get close first time.
chase.ng wrote on Apr 18th, 2006, 6:36am:Hi all,
Just want to know what is the best way to run the post layout simulation. Normally when then first layout comes out, the parasitic will cause the specs to deviate from prelayout simulation, if we want to retune the circuit, do we change the schematic, and then the layout, re-extract and then run the post layout simulation again? Is there any other option? So that the specs will converge faster.
Thank you.
Chase