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VHDL AMS simulation help (Read 1968 times)
Sudhakar
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VHDL AMS simulation help
May 09th, 2006, 2:23am
 
1)Roughly how much improvement in the run time can we expect if the
parameters are defined in the generic rather than as constants in the
architectecture, as far as i know if we declare in the generic in the
entity they are done at the compile time instead of the run time.

2)what difference will it make in the following 2 delcarations  ::
            A)  entity xyz is
                       generic(constant:isat:real:=0.0)
                       port..............
                 end entity
             B) entity xyz is
                       generic(isat:real:=0.0)
                       port..............
                 end entity
if u look at the 2 entity definitions in the earlier theres isat defined
as constant in the entity whereas in the later its not. both work fine ,
iam looking into the speed aspect of the circuits so this subtle
difference in speeds do matter to me.


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